Abstract: A circuit for refreshing memory cells of a dynamic memory contains a refresh control circuit (3, 4, 7) and a memory circuit (2) for storing a plurality of register bits (2-1 to 2-n), a respective one of the register bits being assigned to at least one of the memory cells. In the event of an access to one of the memory cells, a set circuit (6) sets the assigned register bit (2-1 to 2-n), and a reset circuit (5) resets a set register bit (2-1 to 2-n). For controlling a refresh operation of one of the memory cells (MC), the refresh control circuit (3, 4, 7) evaluates the assigned register bit (2-1 to 2-n) and carries out the refresh operation in a manner dependent on the state of said register bit.

Abstract: A method and an apparatus for transmitting data on an internal and/or external transfer path in and/or to a semiconductor component such as a semiconductor memory, in which, a first coder/decoder codes a data sequence by stipulating a signal level of a data signal that is transmitted on a transfer path in sync with a clock signal. A second coder/decoder decodes the transmitted data signal by assessing the signal level in order to ascertain the original data sequence. In addition to the coded data signal, a reference signal block having at least one reference signal level is transmitted. The reference signal level is compared with the signal level of the transmitted coded data signal in the second coder/decoder in order to assess the signal level.

Abstract: An integrated semiconductor memory has regular row and column lines, which can be replaced with redundant row and column lines in the event of a fault. Following initialization of the memory cells with an initialization data item, a data generator circuit writes an identification data item to the memory cells along a regular row or column line. A faulty regular row or column line is replaced with the associated redundant row or column line. Next, the initialization data item is written to memory cells along sound regular row or column lines and the respective identification data item is written to the memory cells along a faulty regular row or column line. Faulty regular row or column lines have the same data value in their memory cells as the redundant row or column lines replacing them.

Abstract: An integrated semiconductor memory includes a memory cell array having memory cells for storing a datum having a first and a second data value. An input datum present at a data terminal is stored multiply in the memory cells of the memory cell array. In order to read out the input datum, the multiply stored input data are fed to an evaluation circuit. The evaluation circuit generates, on the output side, an output datum having the data value that was stored more frequently in the memory cells used for multiple storage of the input datum than other data values. The integrated semiconductor memory thus makes it possible to reduce transfer errors when reading data into the memory cell array or reading data out of the memory cell array.

Abstract: A circuit and a method determine at least one electrical characteristic variable for an integrated circuit. Two or more successively produced states of a reference signal are recorded and counted in a first recording unit to produce an output voltage in a voltage generator circuit for the integrated circuit, and the number of detected states is stored. Furthermore, a time duration within which the states of the reference signal are recorded is recorded in a second recording unit. The numerical values are output via an output circuit for determining the electrical characteristic variable. At least one electrical characteristic variable such as a voltage, current and/or power value for the integrated circuit, is calculated from the number of successively recorded states of the reference signal and from the time duration. It is therefore possible to obtain accurate values relating to the operation of the integrated circuit with comparatively little complexity.

Abstract: An integrated dynamic memory includes a memory cell array having memory cells for storing a charge corresponding to an information bit. The memory cell array has a regular cell area with regular memory cells, a first test cell area with first test cells and a second test cell area with second test cells. A control unit is provided for refreshing the charge contents of the regular memory cells with a first refresh time, a control unit is provided for refreshing the charge contents of the first test cells with a second refresh time, and the charge contents of the second test cells with a third refresh time. The first refresh time is shorter than the second refresh time and the latter is shorter than the third refresh time. An evaluation unit is provided for detecting memory cell defects in the first and second test cell areas.

Abstract: A memory module has an electronic printed circuit board and a plurality of semiconductor memory chips. A series circuit of the semiconductor memory chips is formed with the aid of two leads that can be driven by external contacts of the printed circuit board, and with the aid of connection lines between in each case two semiconductor memory chips. By means of the series circuit, individual semiconductor memory chips can be driven selectively with respect to the rest of the semiconductor memory chips without having to interrupt the regular data transport via the address and control lines. During normal memory operation, chip-specific test data or other data can be interrogated and be read out via an electric loop formed between the further external contacts.

Abstract: An integrated semiconductor memory (1) has a multiplicity of memory cells (Z) and first lines (10) and second lines (20) that can be used to actuate the memory cells (Z). The path of each of the first lines (10) contains a respective device (5) that permits actuation of memory cells exclusively in the region of first subsections (I) of the first lines (10). The devices (5) can be set such that they bring about only partial decoupling of the second subsections (II) of the first lines (10) from the latter s first subsections (I), with memory cells either in the region of the first subsections (I) only or in the region of both subsections (I, II) being able to be actuated, depending on the choice of a relatively short or a relatively long access time to the memory cells. This allows subregions of the semiconductor memory to be used for power-saving and faster memory operation.

Abstract: A semiconductor memory and a method for operating the semiconductor memory store information items at least in triplicate at memory addresses in a plurality of memory areas, preferably memory banks, and read the information items therefrom. A checking unit contains synchronization circuits compares the data values that are read and, if the information items that are read differ, can ascertain and possibly immediately correct storage errors. The method of operating the memory enables quasi-random access to memory cells using a permutation circuit. In a test mode for the semiconductor memory, an error log circuit can output error log data instead of or in addition to data values that are read.

Abstract: A circuit for controlling a refresh rate of memory cells of a dynamic memory includes a control circuit for controlling an access to memory cells of the dynamic memory. A memory circuit can be driven by the control circuit and stores a time information item with regard to an access to a memory cell assigned to the time information item. The control circuit can be operated in a supervisory operating mode such that a time information item is written to the memory circuit by the control circuit in the event of an access to the assigned memory cell. The time information item is read out in the event of a subsequent access to the assigned memory cell.

Abstract: A light guide configuration for serial bi-directional signal transmission includes an optical signal line for carrying electromagnetic radiation along a main direction of the line, optical accesses disposed along the main direction for coupling electromagnetic radiation in and out along a direction running substantially perpendicular to the main direction of the line, and diffusers disposed inside the optical signal line and allocated to an optical access, respectively. Each of the diffusers works in conjunction with the allocated optical access such that a portion of the radiation that is carried in the optical signal line can be coupled out of the optical signal line by the diffuser through the allocated optical access, and radiation entering through the optical access can be coupled into the optical signal line through the allocated diffuser. An optical circuit board having the configuration and a method for fabricating the optical circuit board are also provided.

Abstract: A circuit for refreshing memory cells of a dynamic memory contains a refresh control circuit (3, 4, 7) and a memory circuit (2) for storing a plurality of register bits (2-1 to 2-n), a respective one of the register bits being assigned to at least one of the memory cells. In the event of an access to one of the memory cells, a set circuit (6) sets the assigned register bit (2-1 to 2-n), and a reset circuit (5) resets a set register bit (2-1 to 2-n). For controlling a refresh operation of one of the memory cells (MC), the refresh control circuit (3, 4, 7) evaluates the assigned register bit (2-1 to 2-n) and carries out the refresh operation in a manner dependent on the state of said register bit.

Abstract: A circuit for refreshing memory cells of a dynamic memory contains a refresh control circuit for driving a memory cell array for accessing memory cells of the dynamic memory for a refresh process. Furthermore, a storage circuit is provided, which is assigned to at least one of the memory cells, for storing a time information item with regard to a last previous access to the assigned memory cell during the operation of the memory, a register bit being set in a manner dependent on the stored time information item and being able to be evaluated for controlling a refresh process. The refresh control circuit calls up the time information item stored in the storage circuit during operation of the memory and accesses the memory cell array in such a way that the memory cell assigned to the storage circuit is refreshed in a manner dependent on the time information item.

Abstract: A memory arrangement in a computer system can have at least one memory module with semiconductor components, which are arranged on the memory module, can be operated in parallel and are additionally connected to one another via a serial line. The memory arrangement can have an interface bus for driving the semiconductor components on a module-specific basis, and an interface, which is driven by a memory controller assigned to the memory module via the interface bus and accesses the semiconductor components via the serial line. During normal operation, it is possible to test and adjust the semiconductor components in proximity to the application and on a chip-specific basis via the interface.

Abstract: A semiconductor circuit can have a standard interface for external data, address and/or command interchange in normal operation and a further test interface provided for a test operation with a semiconductor component and with a BIST unit (built-in self-test) assigned to the semiconductor component. The semiconductor circuit can also have a BIST controller for initialization, testing and application-near setting of the semiconductor component, a read-only nonvolatile memory, a programmable nonvolatile memory, and a volatile memory. The processed data stored as operating, test and/or boot parameters in the programmable nonvolatile memory are used during booting and in normal operation for test and configuration purposes for application-near setting of the semiconductor circuit.

Abstract: A flat or sheet-like electrooptical component for sending and receiving electrical and optical signals includes a central emission region with at least one light-emitting device for sending out optical signals. A sensor region is arranged around the emission region, and at least one device for sensing optical signals is configured in the sensor region. A reflector region is arranged around the sensor region for reflecting incident electromagnetic radiation. The electrooptical component also includes a device for driving the light-emitting device based on incoming electrical signals, and a device for outputting electrical signals based on received optical signals.

Abstract: A circuit and a method determine at least one electrical characteristic variable for an integrated circuit. Two or more successively produced states of a reference signal are recorded and counted in a first recording unit to produce an output voltage in a voltage generator circuit for the integrated circuit, and the number of detected states is stored. Furthermore, a time duration within which the states of the reference signal are recorded is recorded in a second recording unit. The numerical values are output via an output circuit for determining the electrical characteristic variable. At least one electrical characteristic variable such as a voltage, current and/or power value for the integrated circuit, is calculated from the number of successively recorded states of the reference signal and from the time duration. It is therefore possible to obtain accurate values relating to the operation of the integrated circuit with comparatively little complexity.

Abstract: A circuit configuration for measuring at least one operating parameter for an integrated circuit includes an analysis circuit connected to at least one external connection on the integrated circuit. The analysis circuit detects a plurality of voltage level changes on the external connection, which is used to control a method of operation for the integrated circuit, in particular, and supplies them to a counter circuit that logs at least one digitally coded value. The coded value is, then, output for analysis purposes to ascertain at least one operating parameter. This, advantageously, allows an average mode of operation for the integrated circuit to be logged during operation of the circuit in the application using parameters and allows respective operating states to be ascertained therefrom.

Abstract: An integrated dynamic memory includes a memory cell array having memory cells for storing a charge corresponding to an information bit. The memory cell array has a regular cell area with regular memory cells, a first test cell area with first test cells and a second test cell area with second test cells. A control unit is provided for refreshing the charge contents of the regular memory cells with a first refresh time, a control unit is provided for refreshing the charge contents of the first test cells with a second refresh time, and the charge contents of the second test cells with a third refresh time. The first refresh time is shorter than the second refresh time and the latter is shorter than the third refresh time. An evaluation unit is provided for detecting memory cell defects in the first and second test cell areas.

Abstract: An integrated dynamic memory includes a memory cell array having memory cells for storing a charge corresponding to an information bit. The memory cell array has a regular cell area with regular memory cells, a first test cell area with first test cells and a second test cell area with second test cells. A control unit is provided for refreshing the charge contents of the regular memory cells with a first refresh time, a control unit is provided for refreshing the charge contents of the first test cells with a second refresh time, and the charge contents of the second test cells with a third refresh time. The first refresh time is shorter than the second refresh time and the latter is shorter than the third refresh time. An evaluation unit is provided for detecting memory cell defects in the first and second test cell areas.