Abstract: A semiconductor module has a plurality of contact terminals used for external data interchange, address interchange and/or command interchange during normal operation of the semiconductor module. The module further has at least one further contact terminal that is not used for external data interchange, address interchange and/or command interchange during normal operation. A mode of operation for ascertaining and outputting test information and, respectively, for configuring the semiconductor module during normal operation of the semiconductor module is initialized and set via a test and configuration circuit, which is connected to the further contact terminal, with data interchange, address interchange and/or command interchange simultaneously being effected during normal operation of the semiconductor module via the contact terminals.

Abstract: A self-test circuit has an address generator unit for generating a test address for the purpose of testing a memory circuit and a control circuit that has signal inputs via which test commands can be applied and via which a memory access may be carried out. A first register is provided for storing an address difference value, in which case, as a result of a first test command, the address generator circuit increases the test address by the address difference value in the event of a subsequent memory access or, as a result of a second test command, the address generator circuit decreases the test address by the address difference value in the event of a subsequent memory access.

Abstract: An integrated memory contains an addressing unit for addressing memory cells for a memory access on the basis of received addressing signals. An addressing calculation logic unit is connected to the addressing unit. The latter can be activated by a test mode signal for a test operation of the memory. The addressing calculation logic unit receives command signals and address signals for the test operation, calculates therefrom the addressing signals for the memory access and feeds the latter into the addressing unit. After an initialization with the loading of initial parameters, the command signals and address signals for the test operation are applied to the addressing calculation logic unit and read/write operations are carried out by an access controller. An integrated memory with implemented BIST hardware, in the case of which a comparatively high functionality and flexibility during the memory test, are nevertheless made possible.

Abstract: A method and a device determine an operating temperature of a semiconductor component during operation, wherein the semiconductor component has a PROM memory area which can be read from the outside. The device further has a programming device for programming the PROM memory area of the semiconductor component in which the operating temperature is obtained by interpolation in between a first calibration temperature value and a second calibration temperature value in dependence from an actual measurement. The device has a multivibrator for generating a measurement signal which has a measuring circuit and a driver circuit. The frequency of the measurement signal depends on the temperature of the measuring circuit in the semiconductor component. A frequency counter for senses the frequency of the measurement signal in a predefined measuring interval.

Abstract: The integrated memory has memory cells in a memory cell block having a plurality of column lines and a plurality of row lines. The row lines include regular row lines and redundant row lines. In the event of a read access to a current row line, a self-test unit checks the correctness of the memory cell contents read and, in the event of a defect, generates a defect signal for the current row line and, for each regular row line, detects the defects ascertained and compares them with an average defect for all of the regular row lines. When a predetermined repair condition is met during the comparison, the self-test unit outputs a row repair signal for the current row line. A self-repair unit interacting with the self-test unit replaces the current row line by a redundant row line in response to a row repair signal in the course of operation of the integrated memory. By still utilizing the existing redundancy after delivery, the failure probability of the memory module can be significantly reduced.

Abstract: A semiconductor memory and a method for operating the semiconductor memory store information items at least in triplicate at memory addresses in a plurality of memory areas, preferably memory banks, and read the information items therefrom. A checking unit contains synchronization circuits compares the data values that are read and, if the information items that are read differ, can ascertain and possibly immediately correct storage errors. The method of operating the memory enables quasi-random access to memory cells using a permutation circuit. In a test mode for the semiconductor memory, an error log circuit can output error log data instead of or in addition to data values that are read.

Abstract: An integrated dynamic memory includes a memory cell array having memory cells for storing a charge corresponding to an information bit. The memory cell array has a regular cell area with regular memory cells, a first test cell area with first test cells and a second test cell area with second test cells. A control unit is provided for refreshing the charge contents of the regular memory cells with a first refresh time, a control unit is provided for refreshing the charge contents of the first test cells with a second refresh time, and the charge contents of the second test cells with a third refresh time. The first refresh time is shorter than the second refresh time and the latter is shorter than the third refresh time. An evaluation unit is provided for detecting memory cell defects in the first and second test cell areas.

Abstract: A flat or sheet-like electrooptical component for sending and receiving electrical and optical signals includes a central emission region with at least one light-emitting device for sending out optical signals. A sensor region is arranged around the emission region, and at least one device for sensing optical signals is configured in the sensor region. A reflector region is arranged around the sensor region for reflecting incident electromagnetic radiation. The electrooptical component also includes a device for driving the light-emitting device based on incoming electrical signals, and a device for outputting electrical signals based on received optical signals.

Abstract: The invention relates to a method and a device for for [sic] determining an operating temperature of a semiconductor component during operation, the semiconductor component comprising a PROM memory area which can be read from the outside, and a programming device for programming the PROM memory area of the semiconductor component.

Abstract: A light guide configuration for serial bi-directional signal transmission includes an optical signal line for carrying electromagnetic radiation along a main direction of the line, optical accesses disposed along the main direction for coupling electromagnetic radiation in and out along a direction running substantially perpendicular to the main direction of the line, and diffusers disposed inside the optical signal line and allocated to an optical access, respectively. Each of the diffusers works in conjunction with the allocated optical access such that a portion of the radiation that is carried in the optical signal line can be coupled out of the optical signal line by the diffuser through the allocated optical access, and radiation entering through the optical access can be coupled into the optical signal line through the allocated diffuser. An optical circuit board having the configuration and a method for fabricating the optical circuit board are also provided.

Abstract: The integrated memory has memory cells in a memory cell block having a plurality of column lines and a plurality of row lines. The row lines include regular row lines and redundant row lines. In the event of a read access to a current row line, a self-test unit checks the correctness of the memory cell contents read and, in the event of a defect, generates a defect signal for the current row line and, for each regular row line, detects the defects ascertained and compares them with an average defect for all of the regular row lines. When a predetermined repair condition is met during the comparison, the self-test unit outputs a row repair signal for the current row line. A self-repair unit interacting with the self-test unit replaces the current row line by a redundant row line in response to a row repair signal in the course of operation of the integrated memory. By still utilizing the existing redundancy after delivery, the failure probability of the memory module can be significantly reduced.

Abstract: A method and an apparatus for transmitting data on an internal and/or external transfer path in and/or to a semiconductor component such as a semiconductor memory, in which, a first coder/decoder codes a data sequence by stipulating a signal level of a data signal that is transmitted on a transfer path in sync with a clock signal. A second coder/decoder decodes the transmitted data signal by assessing the signal level in order to ascertain the original data sequence. In addition to the coded data signal, a reference signal block having at least one reference signal level is transmitted. The reference signal level is compared with the signal level of the transmitted coded data signal in the second coder/decoder in order to assess the signal level.