Abstract: A package (2) comprises a box body (4) with an open end (22) at the top, a tongue-lid (6) adapted to close the open end (22), rotatably connected to a rear edge of the open end (22) by a lid hinge (30), and an inner pack (8) enclosed in the box body (4). The inner pack (8) includes an envelope (13) enclosing tobacco items (10) and keeping the inner pack (8) airtight.

Abstract: The package (2) has an inner case (7) having a box body (6) with an open end (22) in an upper portion and a lid (4) that is connected to a first side edge of the open end (22) and turns about a lid hinge (24) to open/close the open end (22); and an outer slider (8) that is slidably fitted in a periphery of the inner case (7), the outer slider (8) having a contact flap (48) extending towards the inside of the outer slider (8) in an upper edge (50) of a first side wall (44) corresponding to the lid hinge (24). The inner case (7) includes a band-like member (34), which is connected to the lid (4) at the upper end thereof and has a folded flap (38) engageable with the contact flap (48) of the outer slider (8) in a lower end thereof. When the outer slider (8) is slid down in relation to the inner case (7), the folded flap (38) is engaged with the contact flap (48) and opens the lid (4).

Abstract: A slide action type hinged-lid package (2) includes an inner case (6) having a lid (4), and an outer body (8) slidably accommodating the inner case. The outer body has an opening (46) formed through a front wall thereof (40) and allowing the inner case to be partly exposed, and a contact piece (48) provided at the rear edge of an upper open end thereof (38) and extending toward the interior of the outer body. The inner case has a reinforcing member arranged on the inside of a front wall thereof (14) which is exposed through the opening, and a strip (34) connected to the rear part of the lid and capable of engaging with the contact piece. When the inner case is slid up relative to the outer body, the engagement between the strip and the contact piece causes the lid to open and also regulates the amount of sliding of the inner case.

Abstract: A volume chamber is formed by a valve member, an inner peripheral wall of a tubular portion and a bottom portion of a stopper when the valve member is engaged with tubular portion. A communication passage communicates between the volume chamber and one of an intermediate passage of a valve body and a tertiary passage of the stopper. The communication passage is formed at a location, which is spaced from a contact surface between the tubular portion and the valve member by a first predetermined distance and is also spaced from a contact surface between the bottom portion and the first urging member by a second predetermined distance.

Abstract: On one side of a passageway for an identification subject 10 with an IC tag 7 to pass, an antenna is provided for reading information stored in the IC tag 7, and a front wave-absorbing wall 2 and a rear wave-absorbing wall 3 are provided protruding from the vicinity of the front and rear edges of the antenna 8 toward the passageway 13 such that the walls narrow the half-power angle ? of the radio wave radiated from the antenna 8 over a horizontal plane. A wave-absorbing side wall 1 is also provided on the other side of the passageway 13. With such a structure, the propagation area of the radio wave can be controlled so that the reading area of the IC tag 7 can be limited, and the influence of the reflected wave is suppressed.

Abstract: Delay distribution in an integrated circuit is calculated while taking into account a correlation of performance between interconnects or elements in the integrated circuit, thereby improving estimation accuracy. Circuit information, performance distribution information of the interconnects or elements in the integrated circuit, and correlation information of performance between the interconnects or elements are input. A vertex is selected for calculation, and a correlation between delay distribution at the selected vertex and delay distribution in a partial circuit including the selected vertex is calculated based on the performance distribution information and the correlation information.

Abstract: Delay distribution in an integrated circuit is calculated while taking into account a correlation of performance between interconnects or elements in the integrated circuit, thereby improving estimation accuracy. Circuit information, performance distribution information of the interconnects or elements in the integrated circuit, and correlation information of performance between the interconnects or elements are input. A vertex is selected for calculation, and a correlation between delay distribution at the selected vertex and delay distribution in a partial circuit including the selected vertex is calculated based on the performance distribution information and the correlation information.

Abstract: The invention provides a low-pass filter suitably used as a loop filter for a PLL or a DLL that has a filtering characteristic equivalent to that of a conventional one and can be realized in a smaller circuit area. The low-pass filter includes first filtering means (31) for accepting, as an input, an input signal to the low-pass filter and outputting a first voltage; a circuit element (311) included in the first filtering means (31) for allowing a first current to flow in accordance with the first voltage; current generating means (32) for generating a second current at a given rate to the first current; second filtering means (33) for accepting, as an input, the second current and outputting a second voltage; and adding means (34) for adding the first voltage and the second voltage and outputting an output signal of the low-pass filter, in which the second current is set to be smaller than the first current.

Abstract: The invention provides a low-pass filter suitably used as a loop filter for a PLL or a DLL that has a filtering characteristic equivalent to that of a conventional one and can be realized in a smaller circuit area. The low-pass filter includes first filtering means (31) for accepting, as an input, an input signal to the low-pass filter and outputting a first voltage; a circuit element (311) included in the first filtering means (31) for allowing a first current to flow in accordance with the first voltage; current generating means (32) for generating a second current at a given rate to the first current; second filtering means (33) for accepting, as an input, the second current and outputting a second voltage; and adding means (34) for adding the first voltage and the second voltage and outputting an output signal of the low-pass filter, in which the second current is set to be smaller than the first current.

Abstract: In placement of 6-bit interconnection lines in parallel, for example, interconnection lines for three lower-order bits having a high signal change frequency and interconnection lines for three higher-order bits having a low signal change frequency are placed alternately, so that each interconnection line for a lower-order bit is sandwiched by interconnection lines for higher-order bits. With this layout, the interconnection lines for higher-order bits serve like shield lines for the interconnection lines for lower-order bits. This effectively suppresses increase in delay in signal propagation due to change of a signal propagating through an interconnection line for a lower-order bit and a signal propagating through an interconnection line for a higher-order bit to opposite phases, without increasing the area.

Abstract: A physical design method optimizes the performance of an integrated circuit much more efficiently. After an initial layout is obtained for an integrated circuit, a set of process steps, including evaluating the overall performance of the integrated circuit, selecting a candidate cell and changing the performance of the cell, is carried out a number of times. In the step of selecting a candidate cell, a cell, which should have its performance changed, is selected from multiple cells included in the integrated circuit based on the performance evaluation result obtained. Then, by reference to a library, a characteristic representing the performance of the candidate cell is determined in accordance with an external condition imposed thereon.

Abstract: Delay distribution in an integrated circuit is calculated while taking into account a correlation of performance between interconnects or elements in the integrated circuit, thereby improving estimation accuracy. Circuit information, performance distribution information of the interconnects or elements in the integrated circuit, and correlation information of performance between the interconnects or elements are input. A vertex is selected for calculation, and a correlation between delay distribution at the selected vertex and delay distribution in a partial circuit including the selected vertex is calculated based on the performance distribution information and the correlation information.

Abstract: Circuit information supplied in an encrypted state (supplied circuit information) is decrypted by a supplied circuit information decrypting section and then encrypted by a stored circuit information encrypting section, to be stored in a storage section as stored circuit information. The stored circuit information is decrypted by a stored circuit information/intermediate data decrypting section and is input to a simulator engine, thereby performing a simulation. Intermediate data generated during the simulation is encrypted by an intermediate data encrypting section, stored in the storage section, decrypted also by the stored circuit information/intermediate data decrypting section, and then input to the simulator engine. In this manner, the simulation is easily performed, while enhancing the confidentiality of the circuit information.

Abstract: In placement of 6-bit interconnection lines in parallel, for example, interconnection lines for three lower-order bits having a high signal change frequency and interconnection lines for three higher-order bits having a low signal change frequency are placed alternately, so that each interconnection line for a lower-order bit is sandwiched by interconnection lines for higher-order bits. With this layout, the interconnection lines for higher-order bits serve like shield lines for the interconnection lines for lower-order bits. This effectively suppresses increase in delay in signal propagation due to change of a signal propagating through an interconnection line for a lower-order bit and a signal propagating through an interconnection line for a higher-order bit to opposite phases, without increasing the area.

Abstract: Delay distribution in an integrated circuit is calculated while taking into account a correlation of performance between interconnects or elements in the integrated circuit, thereby improving estimation accuracy. Circuit information, performance distribution information of the interconnects or elements in the integrated circuit, and correlation information of performance between the interconnects or elements are input. A vertex is selected for calculation, and a correlation between delay distribution at the selected vertex and delay distribution in a partial circuit including the selected vertex is calculated based on the performance distribution information and the correlation information.

Abstract: In an automatic routing/designing process of an LSI using a maze algorithm, multiple sub-regions, formed by getting a grid column partitioned by a component placed in a routing region, are extracted. And grid point availability, representing the number of grid points available for routing, is obtained for each of these sub-regions. Also, if there is any open net, then the component is vertically moved upward by one grid unit, for example, to make the net routable. If the grid point availability of a sub-region, used for routing another net, has become negative as a result of the movement of the component, then the net is rerouted to pass other sub-regions. Accordingly, even if a height constraint, for example, has been imposed on the routing region, all of the nets can be routed successfully with the constraint satisfied without increasing the number of grid points in the column direction. As a result, the number of open nets can be minimized and all of the nets are much more likely to be routed successfully.

Abstract: There is no conventional method for precisely estimating under what external conditions each partial circuit, such as a library cell, is utilized in an actual integrated circuit at the time of designing the partial circuit. Therefore, by estimating the external conditions of a partial circuit when used in an integrated circuit so that the partial circuit is designed in accordance with the external conditions, the partial circuit having optimal performance for the external conditions can be designed.

Abstract: A layout structure and a method for generating a layout for an integrated circuit more efficiently to catch up with remarkable developments of fabrication technologies of today. In generating a layout for a CMOS circuit, a pair of p- and n-channel transistors is used as a layout unit if one of these transistors is the dual of the other. These two transistors of are placed closely to each other so that when wires are connected to the source or drain of the p-channel transistor and to the source or drain of the n-channel transistor, those wires can be extended substantially vertically to each other.

Abstract: A facing direction confirming device for a head of a golf club to shoot a golf ball accurately in an intended direction, a method of forming an index of the facing direction of the club head. and a golf club having a club head with the index are disclosed. The confirming device includes a mat, a light source mounted on a first end of the mat for emitting a light beam, a reflecting mirror mounted on an opposite, second end for confining the direction of the light beam, a ball target interposed close to the light source between the light source and the reflecting mirror, and a transparent plate interposed between the light source and the ball target for detecting a light spot reflected from the reflecting mirror.