Abstract: In placement of 6-bit interconnection lines in parallel, for example, interconnection lines for three lower-order bits having a high signal change frequency and interconnection lines for three higher-order bits having a low signal change frequency are placed alternately, so that each interconnection line for a lower-order bit is sandwiched by interconnection lines for higher-order bits. With this layout, the interconnection lines for higher-order bits serve like shield lines for the interconnection lines for lower-order bits. This effectively suppresses increase in delay in signal propagation due to change of a signal propagating through an interconnection line for a lower-order bit and a signal propagating through an interconnection line for a higher-order bit to opposite phases, without increasing the area.

Abstract: Delay distribution in an integrated circuit is calculated while taking into account a correlation of performance between interconnects or elements in the integrated circuit, thereby improving estimation accuracy. Circuit information, performance distribution information of the interconnects or elements in the integrated circuit, and correlation information of performance between the interconnects or elements are input. A vertex is selected for calculation, and a correlation between delay distribution at the selected vertex and delay distribution in a partial circuit including the selected vertex is calculated based on the performance distribution information and the correlation information.

Abstract: In designing an integrated circuit, the size of a transistor is optimized together with the folding number thereof. The optimization of the size and folding number of the transistor is accomplished by using a folding model in which a plurality of folding numbers are assumed for one transistor size. In the folding model, if the lower limit value of the transistor size W is W0 and the height of a placement region for the transistor is H0, the folding number N can be determined arbitrarily so long as W/H0≦N≦W/W0 is satisfied. If the size of the transistor is optimized together with the folding number thereof by using the folding model so long as a given design constraint is satisfied, there can be designed an integrated circuit which has been improved in terms of area and performance.

Abstract: The present invention realizes the optimization of a transistor size with higher precision and in a shorter time, in designing a layout for an integrated circuit. A diffusion sharing estimation section estimates a diffusion-sharing region in the layout of the integrated circuit based on circuit data. A circuit characteristic evaluation section evaluates the characteristics, such as area, delay and power consumption, of the integrated circuit in accordance with the information about the diffusion-sharing region estimated by the diffusion sharing estimation section. A transistor size optimization section sets various size candidates for each of the transistors, which constitute the integrated circuit, provides these size candidates to the diffusion sharing estimation section and the circuit characteristic evaluation section, and then selects an optimum transistor size from the transistor size candidates thus set in accordance with the evaluation results obtained by the circuit characteristic evaluation section.

Abstract: Method and apparatus for suppressing change in wiring delay time resulting from cell interchange and thereby satisfying required specifications in a short period of time with certainty during LSI layout designing. Cells are arranged in parallel to each other and routed based on circuit designing information, thereby designing a block layout including a plurality of cell rows. A cell not satisfying the required specifications is extracted from the block layout, and a level of drivability required for the cell to satisfy the required specifications is calculated. The extracted cell in question is interchanged with a substitute cell. The substitute cell has equivalent logic, a required level of drivability and the same width and terminal position in the cell arrangement direction reaction a cell row as the counterparts of the cell in question and is provided in a stretchable cell library.

Abstract: First, initial routing is performed on a net. If a design rule error exists in a wire already routed as a result of the initial routing, the wire already routed, causing the design rule error, is removed. Next, if the wire already routed and removed is a wire interconnecting a movable terminal, freely placeable within a predetermined region, to another terminal, then the movable terminal is displaced within the predetermined region and the removed wire is re-routed such that the displaced movable terminal is interconnected to the other terminal. Accordingly, the movable terminal can be located at an appropriate position within the predetermined region in accordance with the situation of surrounding wires. As a result, routing results of a higher density can be obtained.

Abstract: Method and apparatus for suppressing change in wiring delay time resulting from cell interchange and thereby satisfying required specifications in a short period of time with certainty during LSI layout designing. Cells are arranged in parallel to each other and routed based on circuit designing information, thereby designing a block layout including a plurality of cell rows. A cell not satisfying the required specifications is extracted from the block layout, and a level of drivability required for the cell to satisfy the required specifications is calculated. The extracted cell in question is interchanged with a substitute cell. The substitute cell has equivalent logic, a required level of drivability and the same width and terminal position in the cell arrangement direction on a cell row as the counterparts of the cell in question and is provided in a stretchable cell library.

Abstract: There is no conventional method for precisely estimating under what external conditions each partial circuit, such as a library cell, is utilized in an actual integrated circuit at the time of designing the partial circuit. Therefore, by estimating the external conditions of a partial circuit when used in an integrated circuit so that the partial circuit is designed in accordance with the external conditions, the partial circuit having optimal performance for the external conditions can be designed.

Abstract: The invention provides a functional module model for realizing optimal pipelining. The functional module model includes division line data representing division lines corresponding to positions where pipeline registers can be inserted and delay/area data representing the trade-off relationship between the delay and the area of each division area partitioned by the division lines. By using this functional module model, a pipeline register insertion position is selected among the division lines represented by the division line data, and the delay and the area of each division area are set on the basis of the trade-off relationship represented by the delay/area data. Thus, a pipelined circuit with a minimized area can be synthesized.

Abstract: A physical design method optimizes the performance of an integrated circuit much more efficiently. After an initial layout is obtained for an integrated circuit, a set of process steps, including evaluating the overall performance of the integrated circuit, selecting a candidate cell and changing the performance of the cell, is carried out a number of times. In the step of selecting a candidate cell, a cell, which should have its performance changed, is selected from multiple cells included in the integrated circuit based on the performance evaluation result obtained. Then, by reference to a library, a characteristic representing the performance of the candidate cell is determined in accordance with an external condition imposed thereon.

Abstract: The remote power management system of information processing apparatus or the like solves problems as to occurrence of uncontrollability of power supply due to malfunction of an uninterruptible power supply device that is incapable of trying restart and recovery of information processing apparatus of the certain type merely through start or termination of power supply or alternatively as to unwanted interruption of power supply to information processing apparatus constituting a network. The system comprises a remote power switch for change over between turn-on and turn-off of a power supply line, information processing apparatus or network equipment for receiving electrical power form the power supply line via the power switch, and a remote control device for controlling changeover of the remote power switch from a remote location wherein these are connected together over a network.

Abstract: An equivalent circuit converter reads out transistor-level circuit diagram data and equivalency conversion rule data, converts circuit data based on the equivalency conversion rule data, and then feeds back the converted circuit data to the circuit diagram data. An estimate calculator reads out the circuit diagram data, which has been converted by the equivalent circuit converter, and environmental variable data, thereby calculating an estimate representing a degree of optimization. In response to the estimates supplied from the estimate calculator, a circuit optimizer selects partial circuits to be subjected to equivalent circuit conversion during the optimization of the circuit. Then, the circuit optimizer sequentially determines whether or not each of the partial circuits should be converted into an associated equivalent circuit, thereby optimizing the entire circuit.

Abstract: A functional-level processing unit converts a data path diagram into logic circuit data. A logic-level processing unit specifies cells in a data path circuit based on the logic circuit data. A synthesis processing unit uses geometrical functions of the cells which have been parameterized by delays thereof, thereby synthesizing a layout module for the data path circuit based on the logic circuit data used to specify the cells and on a floorplan for the module. The synthesis processing unit also obtains a geometrical function parameterized by delay for the layout module. By synthesizing a layout module using the geometrical functions of the cells, which have been parameterized by the delays thereof, the geometry of the layout module can be optimized with high accuracy. In addition, by generating a geometrical function for the layout module, it becomes easier to establish a linkage to the upper process of design.

Abstract: In designing a layout for a deep-submicron semiconductor integrated circuit, a violational wire involving a violation of the delay limitation is extracted based on information representing a layout result obtained in a layout step. In order to extend a wire spacing between such an extracted wire and its neighboring wire to above a predetermined wire spacing, the neighboring wire is subjected to parallel displacement. If such a parallel displacement causes a distance of separation between the parallelly-displaced wire and its neighboring component to fall below a predetermined distance of separation, the component in question is shifted in order of extending the separation distance. Accordingly, even if the delay time of wire is dominant in comparison with that of element in regard to the signal propagation delay time, violations of the delay limitation occurring when the signal propagation delay time is less than a predetermined delay time can be canceled by a less number of steps.

Abstract: Elements such as a transistor having a terminal corresponding to a wire junction are abstracted by using rectangles, and a spit penetrating these rectangles is introduced in a layout area where the rectangles are disposed. On the spit, a wire junction for allocating a wire is provided. The terminals of the rectangles corresponding to the wire junctions and the wire junctions on the spit are set as net targets, and connection information on these net targets is generated. A scan line for scanning the layout area from its left end to its right end and a front for tracing the net targets are introduced. While conducting rightward scanning by the scan line, the front is proceeded from one net target to the other net target. The trace of the front is provided as a wire element.

Abstract: To reduce a circuit block in area, the present invention provides an LSI layout design method having a cell changing processing for reducing a pure wiring zone in area.By an input processing, circuit design information and cell library are entered. Then, a layout of cells arranged in a plurality of cell rows is designed by a cell placing processing. Then, the height of a wiring zone required between cell rows is estimated by a wiring zone height estimating processing. To reduce the area of a pure wiring zone other than the over-the-cell wiring zones, each of placed cells is changed, by a cell changing processing, to a cell having the same specifications and a different shape or a different terminal position. A layout of cell interconnection is designed by a wiring processing. Based on the layout thus obtained by the processings above-mentioned, a mask pattern is prepared and supplied by a mask pattern preparing processing.

Abstract: Densely-packed leaf cells for semiconductor integrated circuits are generated. The placement of transistors in a leaf cell is determined, and wire routings between the transistors are found on a gridded plane, and a compaction operation is performed on a placement/wiring result on the gridded plane. More specifically, locations of transistors in a leaf cell are determined (i) by a step of initializing a transistor grouping arranged in accordance with diffusion sharing, (ii) by a step of modifying the transistor grouping, (iii) by a step of finding locations of transistor in the modified transistor grouping, (iv) by a step of evaluating a result of the step (iii); and (v) by a step of making a judgment of whether to accept a result of step (iii) according to a result of step (iv).

Abstract: A gate wire is formed so as to extend from an active area to a separation, and an impurity diffused area is formed on each side of the gate electrode located on the active area. A contact member for connecting the gate wire to a first layer aluminum interconnection formed in an upper layer of the gate wire is in contact with the gate wire at a portion located on the active area. The utilization ratio of the active area is thus improved, and hence, the width of the separation can be minimized. In addition, by eliminating a mask alignment margin from the gate wire and suppressing the width of the gate wire not to exceed the width of the contact member, the occupied area of a semiconductor apparatus can be reduced.

Abstract: This invention discloses a method of estimating power dissipation in an electrical circuit formed by a plurality of elements and a plurality of signal lines for input/output transfer. The probability that an output signal makes a transition in response to a change in an input signal is found. Based on this, a formula is found which expresses the output signal transition probability as a function of the input signal transition probability. This method has the following steps. An input signal transition probability is given. By making use of the formula, an output signal transition probability is found in relation to an input signal having the given signal transition probability. Estimation of power dissipation is performed by summing products obtained by multiplying each transition probability by each signal line's load. Computation of the signal transition probability starts at the input side. As a result of such arrangement, power dissipation can be estimated from each signal transition probability.

Abstract: A method is provided for designing a semiconductor integrated circuit device with optimized shape of blocks to minimize the size of the chip containing the circuit. Design restrictions on the shape and position of each block are determined according to the density of temporary paths for electrical connections between blocks and the shape of each side of each block is optimized within the restrictions. The internal layout of each block is then optimized according to the restrictions.