Abstract: Methods and apparatus provide for loading at least one software program module from a storage medium into a local memory of a processor for execution, the storage medium containing a main module and a plurality of sub-modules of the software program; and updating an address table, copies of the address table being located in at least one of the storage medium and the local memory, and the address table having at least one entry for each of the modules, each entry including at least one of: (i) a destination address representing an address within the local memory of a processor at which the corresponding module is disposed, and (ii) a source address representing an address within the storage medium at which the corresponding module originates.

Abstract: Methods and apparatus provide for placing an apparatus into at least one of a plurality of operational modes, wherein: the apparatus includes a local memory, a bus operable to carry information to and from the local memory, one or more arithmetic processing units operable to process data and operatively coupled to the local memory, and a security circuit operable to place the apparatus into the operational modes; and the plurality of operational modes includes: (i) a first mode whereby the apparatus and an external device are operable to initiate a transfer of information into or out of the memory over the bus, (ii) a second mode whereby neither the apparatus nor the external device are operable to initiate a transfer of information into or out of the memory over the bus, and (iii) a third mode whereby the apparatus is operable to initiate a transfer of information into or out of the local memory over the bus, but the external device is not operable to initiate a transfer of information into or out of the loc

Abstract: A processing element (PE) includes a processing unit (PU) and a number of attached processing units (APUs). The instruction set of each APU is divided a priori into a number of types, each type associated with a different amount of heat generation. Each APU keeps track of the amount of each type of instruction executed over a time period, —the power information, —and provides this power information to the PU. The PU then performs power management as a function of the provided power information from each APU, —such as directing a particular APU to enter an idle state to reduce power consumption.

Abstract: Methods and apparatus for placing a processing unit into one or more of a plurality of operational modes are disclosed wherein: the apparatus includes a local memory, a bus operable to carry information to and from the local memory, one or more arithmetic processing units operable to process data and operatively coupled to the local memory, and a security circuit operable to place the apparatus into the operational modes; and the plurality of operational modes includes a first mode whereby the apparatus and an external device may initiate a transfer of information into or out of the memory over the bus, a second mode whereby neither the apparatus nor the external device may initiate a transfer of information into or out of the memory over the bus, and a third mode whereby the apparatus may initiate a transfer of information into or out of the memory over the bus, but the external device may not initiate a transfer of information into or out of the memory over the bus.

Abstract: A system and method are provided to dedicate one or more processors in a multiprocessing system to performing encryption functions. When the system initializes, one of the synergistic processing unit (SPU) processors is configured to run in a secure mode wherein the local memory included with the dedicated SPU is not shared with the other processors. One or more encryption keys are stored in the local memory during initialization. During initialization, the SPUs receive nonvolatile data, such as the encryption keys, from nonvolatile register space. This information is made available to the SPU during initialization before the SPUs local storage might be mapped to a common memory map. In one embodiment, the mapping is performed by another processing unit (PU) that maps the shared SPUs' local storage to a common memory map.

Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A processing system is provided for processing programs and data. The processing system has a processing unit and multiple sub-processing units. Each sub-processing unit includes a dedicated local memory for storing programs and data. The dedicated local memory of each respective sub-processing unit is not a cache memory. In an alternative, multiple computing devices may connect to one another via a communications network, and each computing device may include at least one processing element having the processing unit and sub-processing units.

Abstract: A display apparatus including a communication line connected to a network, an information acquisition device for acquiring in real time at least information relating to a predetermined site on the network via the communication line, the communication line being held by a communication line holding device. The display apparatus includes a display control device for displaying in real time information relating to a plurality of sites acquired by the information acquisition device, and forming symbols corresponding to the plurality of sites, displaying the symbols three-dimensionally in a contrastable state from each other. The information acquired by the information acquisition device is displayed will a symbol, which corresponds to the site, and the information acquisition device acquires at least one of or a plurality of pieces of information indicating congestion status, update status, response, type, popularity, cost, and links of each site, and congestion status of the network.

Abstract: One or more processors within a computing system and the processor(s)' associated local memories may be operatively connected to a main memory enabling data transfer between the main memory and the local memories, in which the computing system can carry out actions that may include: generating a pause condition for one or more processors within a computing system; pausing the one or more processors; saving data from a local memory of the one or more processors to the main memory; hibernating the one or more processors; restoring power to the one or more processors; transferring the saved data originating from the one or more processors back to one originating processor or to designated destination processors in the computing system.

Abstract: Objects which are created in conformity with the data format of objects to be handled in a virtual world are offered to users on the terminal computers of the users independently of the virtual world. The users transmit the offered objects to a server computer which generates the virtual world, while the server computer stores these objects in association with the operators. Since these objects are recorded in a format which can be interpreted by the server computer for generating the virtual world, they can be handled in the virtual world in the same manner as the other objects which have been defined in the virtual world beforehand. Thus, the users are permitted to use in the virtual world objects which are different from the objects which were defined in the virtual world beforehand.

Abstract: Methods and apparatus provide for: receiving a memory access request for data from a processor of a multi-processor system; determining whether the data of the memory access request is stored in a remote processing system coupled to the multi-processor system over a communications network; requesting the data from the remote processing system; receiving the data from the remote processing system over the communications network; and providing the data to the processor of the multi-processor system.

Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

Abstract: A system configuration includes a processing element (PE), an input/output (I/O) interface device and a shared memory. The PE further includes at least one processing unit (PU) and one, or more, attached processing units (APUs). At least one of the APUs performs an I/O function by reading data from, and writing data to, an external device coupled to the I/O interface device. Data is exchanged between the APU and the I/O interface device via the shared memory using a data level synchronization mechanism.

Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

Abstract: One or more processors within a computing system and the processor(s)' associated local memories may be operatively connected to a main memory enabling data transfer between the main memory and the local memories, in which the computing system can carry out actions that may include: generating a pause condition for one or more processors within a computing system; pausing the one or more processors; saving data from a local memory of the one or more processors to the main memory; hibernating the one or more processors; restoring power to the one or more processors; transferring the saved data originating from the one or more processors back to one originating processor or to designated destination processors in the computing system.

Abstract: Methods and apparatus provide for loading at least one software program module from a storage medium into a local memory of a processor for execution, the storage medium containing a main module and a plurality of sub-modules of the software program; and updating an address table, copies of the address table being located in at least one of the storage medium and the local memory, and the address table having at least one entry for each of the modules, each entry including at least one of: (i) a destination address representing an address within the local memory of a processor at which the corresponding module is disposed, and (ii) a source address representing an address within the storage medium at which the corresponding module originates.

Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

Abstract: Methods and apparatus provide for translating a software program page by page from a first instruction set architecture (ISA) into a second ISA using one or more of a set of processors of a multi-processor system; and executing the translated software program using a dedicated other processor of the multi-processor system.

Abstract: Methods and apparatus provide for assigning an identifier to a DMA command, the identifier for association with an entry of a DMA table containing status information regarding the DMA command; receiving an indication that a DMA data transfer defined by the DMA command has been completed; and updating the status information of the entry of the DMA table associated with the DMA data transfer to indicate that the DMA data transfer has been completed.

Abstract: An image producing device includes two or more vector processors for conducting geometry processing for expressing the respective images in parallel to produce graphic element lists, a graphic processor for conducting graphic processing on the basis of the graphic element lists, and an arbitrator. The graphic processor includes two buffers for storing graphic contexts corresponding to the graphic element lists together with identification information on the graphic contexts, and a unit for reading a specific graphic context from the buffers upon inputting the graphic element lists from the arbitrator to conduct the graphic processing. Each of the vector processors produces the graphic element lists having, as their contents, the identification information of the graphic context specified by the geometry processing assigned to each of the vector processors.