Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

Abstract: A recording medium, recording and information processing apparatus and methods by which efficient processing of data and a high processing speed can be readily achieved at lower cost. A main CPU converts coordinates of a polygon in response to a manual operation of an operation unit by a user and transmits data of the polygon to a programmable packet engine via a main bus. The packet engine calculates a Z value representative of the position of the polygon in the depthwise direction from coordinate values of the apexes of the polygon supplied from the main CPU, divides the polygon into a number of sub-polygons corresponding to the Z value, converts coordinate values of the apexes of the sub-polygons in accordance with a normal vector and curved surface parameters and produces a curved surface composed of the sub-polygons. A graphical processing unit writes pixel data of the sub-polygons produced by the programmable packet engine into a frame buffer and performs rendering processing.

Abstract: Objects which are created in conformity with the data format of objects to be handled in a virtual world, are offered to users on the terminal computers of the users independently of the virtual world. The users transmit the offered objects to a server computer which generates the virtual world, while the server computer stores these objects in association with the operators. Since these objects are recorded in the format which can be interpreted by the server computer for generating the virtual world, they can be handled in the virtual world likewise to the other objects which are defined in the virtual world beforehand. Thus, the users are permitted to use in the virtual world the objects which are different from the objects defined in the virtual world beforehand.

Abstract: A recording medium, recording and information processing apparatus and methods by which efficient processing of data and a high processing speed can be readily achieved at lower cost. A main CPU converts coordinates of a polygon in response to a manual operation of an operation unit by a user and transmits data of the polygon to a programmable packet engine via a main bus. The packet engine calculates a Z value representative of the position of the polygon in the depthwise direction from coordinate values of the apexes of the polygon supplied from the main CPU, divides the polygon into a number of sub-polygons corresponding to the Z value, converts coordinate values of the apexes of the sub-polygons in accordance with a normal vector and curved surface parameters and produces a curved surface composed of the sub-polygons. A graphical processing unit writes pixel data of the sub-polygons produced by the programmable packet engine into a frame buffer and performs rendering processing.

Abstract: An image producing device includes two or more vector processors for conducting geometry processing for expressing the respective images in parallel to produce graphic element lists, a graphic processor for conducting graphic processing on the basis of the graphic element lists, and an arbitrator. The graphic processor includes two buffers for storing graphic contexts corresponding to the graphic element lists together with identification information on the graphic contexts, and a unit for reading a specific graphic context from the buffers upon inputting the graphic element lists from the arbitrator to conduct the graphic processing. Each of the vector processors produces the graphic element lists having, as their contents, the identification information of the graphic context specified by the geometry processing assigned to each of the vector processors.

Abstract: There is provided an image generation apparatus which requires a small amount of data for a draw command and a small capacity for a mixing ratio memory and which is capable of performing full transparent and full opaque processes utilizing a semitransparent process at high speed.

Abstract: There is disclosed an entertainment apparatus on which a program for an older version of the apparatus can be executed. In a normal mode, an MPU(100) operates as a main CPU:and a GP(110) operates as a graphics processor, and an IOP(120) operates as a subprocessor for input and output. In a compatible mode in which a program for an older version of the apparatus is executed, the IOP(120) capable of executing the program for the older version of the apparatus operates as a main CPU, and the MPU(100) and GP(110) emulate a graphics processor for the older version of the apparatus.

Abstract: An image creation device includes: a plurality of geometry processing means for creating at least one drawing element list by performing geometry processing to express images, respectively, in parallel, said plurality of geometry processing means having at least one first geometry processing means to perform tyical geometry processing and at least one second geometry processing in cooperation with another geometry processing means; drawing means to perform drawing processing based on said drawing element list; and control means to selectively adopt a first mode which parallelizes said at least one first geometry processing means and said at least one second geometry processing means and a second mode to lead a processing result of said at least one second geometry processing means to an input of said at least one first geometry processing means.

Abstract: In an information processing apparatus, priorities are assigned to a plurality of central processing units (CPUS) and the CPUs transfer their respective display lists of drawing instructions to a drawing unit on a priority basis. With such a scheme, when a master CPU (Geometry Subsystem 0) is creating a display list (List #0-1) and a drawing unit (a rendering system) is in an idle state, a right to make an access to the drawing unit is handed over to a slave CPU (Geometry Subsystem 1), enabling the slave CPU to supply a display list (List 1-1) created thereby, if any, to the drawing unit. Receiving the display list (List #1-1), the drawing unit starts drawing processing in accordance with List #1-1. As the master CPU completes the creation of the display list (List #0-1), the slave CPU returns the right to make an access to the drawing unit to the master CPU, enabling the master CPU to supply List #0-1 to the drawing unit.

Abstract: A recording medium, recording and information processing apparatus and methods by which efficient processing of data and a high processing speed can be readily achieved at lower cost. A main CPU converts coordinates of a polygon in response to a manual operation of an operation unit by a user and transmits data of the polygon to a programmable packet engine via a main bus. The packet engine calculates a Z value representative of the position of the polygon in the depthwise direction from coordinate values of the apexes of the polygon supplied from the main CPU, divides the polygon into a number of sub-polygons corresponding to the Z value, converts coordinate values of the apexes of the sub-polygons in accordance with a normal vector and curved surface parameters and produces a curved surface composed of the sub-polygons. A graphical processing unit writes pixel data of the sub-polygons produced by the programmable packet engine into a frame buffer and performs rendering processing.

Abstract: In a data processing apparatus, data is transferred in accordance with a meta-instruction embedded in the data. To put it in detail, first of all, a first meta-instruction is read out from an address ADDR0 stored in a tag address register Dn_TADR. Then, data following the first meta-instruction with a length specified by the meta-instruction is transferred. Subsequently, a second meta-instruction stored at an address ADDR2 specified in the first meta-instruction is read out and data following the second meta-instruction with a length specified by the second meta-instruction is transferred. A third next meta-instruction stored at an address ADDR1 specified in the second meta-instruction is further read out and data following the third meta-instruction with a length specified by the third meta-instruction is then transferred.

Abstract: A recording medium, recording and information processing apparatus and methods by which efficient processing of data and a high processing speed can be readily achieved at lower cost. A main CPU converts coordinates of a polygon in response to a manual operation of an operation unit by a user and transmits data of the polygon to a programmable packet engine via a main bus. The packet engine calculates a Z value representative of the position of the polygon in the depthwise direction from coordinate values of the apexes of the polygon supplied from the main CPU, divides the polygon into a number of sub-polygons corresponding to the Z value, converts coordinate values of the apexes of the sub-polygons in accordance with a normal vector and curved surface parameters and produces a curved surface composed of the sub-polygons. A graphical processing unit writes pixel data of the sub-polygons produced by the programmable packet engine into a frame buffer and performs rendering processing.

Abstract: Priorities are assigned to a plurality of central processing units (CPUs) and the CPUs transfer their respective display lists of drawing instructions to a drawing unit on a priority basis. When a master CPU (Geometry Subsystem 0) is creating a display list (List #0-1) and a drawing unit (a rendering system) is in an idle state, a right to make an access to the drawing unit is handed over to a slave CPU (Geometry Subsystem 1), enabling the slave CPU to supply a display list (List 1-1) created thereby, if any, to the drawing unit. Receiving the display list (List #1-1), the drawing unit starts drawing processing in accordance with List #1-1. As the master CPU completes the creation of the display list (List #0-1), the slave CPU returns the right to make an access to the drawing unit to the master CPU, enabling the master CPU to supply List #0-1 to the drawing unit. Receiving the display list (List #0-1), the drawing unit starts drawing processing in accordance with List #0-1.

Abstract: A data processing system wherein picture data in which there is allocated a value representing transparency as a pixel value is transmitted after being compressed in terms of picture data corresponding to a pre-set pre-determined size of a picture area as a unit. Ancillary data specifying whether each pixel of the original picture data of the picture data unit is transparent or opaque is transmitted in correlation with the compressed picture data as the unit. On expansion of the compressed picture data, a pixel set as a transparent pixel by the ancillary data is compulsorily set as a transparent pixel without regard to the expanded picture data.

Abstract: A data format is provided capable of assigning a desired color lookup table (CLUT) to a texture pattern of each polygon drawn on a two-dimensional display screen. Assuming that TPF represents a pixel depth of the texture pattern, when TPF is 00, 01, and 10, the format (CLUT) is applied of a 4-bit mode, an 8-bit mode, and 16-bit mode respectively, whereby its related command is decreased in word length and thus requires less storage in a source video memory.