Abstract: A module, for mounting a driver IC constituting a drive circuit of a display apparatus using a flat display panel, is disclosed, which includes a driver IC chip for driving the display electrodes of the flat display panel and a wiring board electrically connected with the driver IC chip. A module for mounting the driver IC having this configuration comprises a first wiring unit formed with a drive power source system wiring for supplying a power source voltage, which is input to the driver IC chip, for driving the flat display panel through the driver IC chip; a second wiring unit formed with a control system wiring for supplying various signals, which are input to the driver IC chip, for controlling the driver IC chip; and a third wiring unit formed with an output terminal wiring taken out from the driver IC chip and connecting to the display electrodes of the flat display panel.

Abstract: A user of a first device may select at least one multimedia presentation. Based on this selection, the multimedia presentation is accessed from a storage source and presented to the user. Simultaneously, information is transmitted to at least a second device that causes the selected multimedia presentation to be presented by the at least second device without the at least second device receiving input from a second user. Continuous media streams from the first user may be captured and transmitted to the second device(s). The presenting of the multimedia presentation on the first device are coordinated with the presenting of the multimedia presentation on the second device(s). The presenting of the captured media streams on the second device(s) are coordinated with the capturing of those streams and the presenting of the multimedia presentation on the second device(s). Users may control the multimedia presentations and the captured media streams.

Abstract: A gate electrode having a first insulating film laminated in the upper portion thereof is formed on a gate insulating film formed on a semiconductor substrate. A side wall is formed on the side wall of the gate electrode, and an insulating film is formed to cover the gate electrode and the side wall. Ion implantation is performed through the insulating film so that a diffusion layer is formed on the semiconductor substrate. An interlayer dielectric film is formed, and then the interlayer dielectric film and the insulating film are selectively etched so that an opening portion for exposing the gate insulating film is formed in a self-align manner with the gate electrode. Then, the gate insulating film in the bottom portion of the opening portion is removed so that the surface of the semiconductor substrate is exposed. Then, a wiring layer connected to the exposed surface of the semiconductor substrate is formed.

Abstract: A highly reliable and highly characteristic semiconductor memory device capable of being subjected to a heat treatment process at a necessary temperature after forming a ferroelectric capacitor and wiring is provided. In Series connected TC unit ferroelectric RAM, a first contact portion of one of source/drain diffusion layers and a lower electrode and a second contact portion of an upper electrode and the other of the source/drain diffusion layers and are formed of a first oxidation resistant conductive film and a second oxidation resistant conductive film, respectively. By utilizing a memory cell block structure proper to the Series connected TC unit ferroelectric RAM, on a capacitor, provided is a hydrogen blocking film having an opening defined in a region without a memory cell, the region being present for each memory cell block.

Abstract: The present invention relates to a driver IC packaging module and a parallel plate type display device incorporating the same, and a chassis structure for an IC module having a high heat radiation effect or a flat display device having a high heat radiation efficiency can be achieved.

Abstract: A process for eliminating roughness on a silicon nitride trench liner is disclosed. A capping film on the top of the trench is formed in a self-aligned manner. This capping film prevents short circuits between a storage node and a passing word-line.

Abstract: A semiconductor memory device includes a semiconductor substrate having convex and concave portions locally formed in a surface thereof. An anti-reflection film serves as a first mask member and is formed on the semiconductor substrate. A photoresist is formed on the anti-reflection film. The anti-reflection film is partially removed using an opening formed by patterning the photoresist so as to expose an upper surface of the convex portion. The convex portion is etched using the photoresist and the anti-reflection film left in the concave portion. The anti-reflection film and the photoresist are removed, thereby obtaining the semiconductor substrate worked in a self-alignment manner.

Abstract: A semiconductor memory device comprises a memory cell region having an array of plurality of memory cells, and a peripheral circuit region to which a bit line connected to a predetermined number of the memory cells in the memory cell region is extended and connected, the bit line in the memory cell region and the bit line in the peripheral circuit region having substantially the same upper surface height.

Abstract: A process for eliminating roughness on a silicon nitride trench liner is disclosed. A capping film on the top of the trench is formed in a self-aligned manner. This capping film prevents short circuits between a storage node and a passing word-line.

Abstract: In a stack type memory cell of 8F2, bit line plug electrodes for connecting bit lines to source/drain diffusion layers of active regions in an area between two word lines WL are formed extend from the source/drain diffusion layers in parallel to the word lines WL and formed longer than the minimum element isolation width F and shorter than three times the minimum element isolation width F. Thus, a DRAM which uses stack type memory cells and whose integration density can be easily enhanced can be attained.

Abstract: A semiconductor memory device comprises a memory cell region having an array of plurality of memory cells, and a peripheral circuit region to which a bit line connected to a predetermined number of the memory cells in the memory cell region is extended and connected, the bit line in the memory cell region and the bit line in the peripheral circuit region having substantially the same upper surface height.

Abstract: An air filter suitably usable in an air cleaner, room air-conditioner or especially in car air-conditioners in which air is driven at a high speed. The air filter is made of a pleated polyurethane foam having on one or both sides thereof a three-dimensional network skeletal structure of micro cells.

Abstract: A method of manufacturing a semiconductor device, comprises the steps of forming a first transfer pattern corresponding to a mask pattern on a major surface side of a semiconductor substrate through a first mask plate on which the first mask pattern having a straight portion and a bent portion is formed, and forming a second transfer pattern corresponding to a second mask pattern on a major surface side of the semiconductor substrate through a second mask plate on which the second mask pattern having a pattern arranged at a position corresponding to the straight portion is formed.

Abstract: A gate electrode having a first insulating film laminated in the upper portion thereof is formed on a gate insulating film formed on a semiconductor substrate. A side wall is formed on the side wall of the gate electrode, and an insulating film is formed to cover the gate electrode and the side wall. Ion implantation is performed through the insulating film so that a diffusion layer is formed on the semiconductor substrate. An interlayer dielectric film is formed, and then the interlayer dielectric film and the insulating film are selectively etched so that an opening portion for exposing the gate insulating film is formed in a self-align manner with the gate electrode. Then, the gate insulating film in the bottom portion of the opening portion is removed so that the surface of the semiconductor substrate is exposed. Then, a wiring layer connected to the exposed surface of the semiconductor substrate is formed.

Abstract: A semiconductor memory device comprises a MOS-type transistor formed on a semiconductor substrate, a capacitor formed in the interior of an opening portion formed in the semiconductor substrate to be adjacent to the MOS-type transistor, the capacitor having a capacitor insulating film formed of a high dielectric film, and a line layer for connecting respective gate electrodes of the MOS-type transistor separated to be island-shaped to prevent from being presented on a region where the opening portion is formed, the line layer formed of a conductive layer different from the gate electrodes in its level.

Abstract: In a stack type memory cell of 8F.sup.2, bit line plug electrodes for connecting bit lines to source/drain diffusion layers of active regions in an area between two word lines WL are formed extend from the source/drain diffusion layers in parallel to the word lines WL and formed longer than the minimum element isolation width F and shorter than three times the minimum element isolation width F. Thus, a DRAM which uses stack type memory cells and whose integration density can be easily enhanced can be attained.

Abstract: The present invention provides a method for forming a resist pattern which allows a closest pattern to be formed thus solving a problem of misalignment. A substrate has, on the surface thereof, first and second domains having different reflectivity to first light. A resist covers the first and second domains. The first light illuminates the resist and reflects from the surfaces of the first and second domains. A resist pattern forms in the fashion of self-alignment based on the illuminated and reflected light. The sum of the exposure of the illuminated and reflected light is set above a threshold of exposure by which the resist is sensitized in the first domain and set below the threshold of exposure in the second domain.

Abstract: A manufacturing method of semiconductor devices and semiconductor devices isolated by a trench portion. The trench portion is refilled with a Si epitaxial growth layer. The trench has a first insulating layer on its side wall and a second insulating layer formed by the oxidation in the self-alignment manner, as a cap layer, on the top portion of the trench. A semiconductor device formed on the substrate is isolated by the trench. The excessive leakage currents created by the stress between the substrate and the Si epitaxial layer are decreased. The concentration of the field effect at the corner portion of the trench is suppressed by the cap layer.The refilling step can be also made to a trench having the wider opening and another trench having the narrower opening simultaneously and uniformly.

Abstract: An air filter suitably usable in an air cleaner, room air-conditioner or especially in car air-conditioners in which air is driven at a high speed. The air filter is made of a pleated polyurethane foam having on one or both sides thereof a three-dimensional network skeletal structure of micro cells.

Abstract: A semiconductor memory device comprises a semiconductor substrate having a plurality of trenches selectively formed thereon, a plurality of capacitors formed in the trenches, each of the capacitors formed of the substrate, a capacitor insulating film formed on a surface of each of the trenches, and a storage node buried in each of the trenches interposing the capacitor insulating film, a plurality of transistors, formed on the substrate, for forming memory cells in relation to the plurality of capacitors, each of the transistors having a gate electrode formed on the substrate interposing a gate insulating film and source and drain regions formed in the substrate on both sides of the gate electrode, a plurality of element isolation films formed on side surfaces of upper portions of the trenches to surround the circumference thereof, respectively, the element isolation films having adjacent ones of the isolation films selectively coupled to each other such that at least one of the transistors is electrically in