Patents by Inventor Masanobu Saito
Masanobu Saito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20010042873Abstract: A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (Tox) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the gate electrode (2) is determined to be equal to or less than 0.3 &mgr;m; and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.5 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.Type: ApplicationFiled: April 9, 2001Publication date: November 22, 2001Inventors: Hisayo Momose, Hiroshi Iwai, Masanobu Saito, Tatsuya Ohguro, Mizuki Ono, Takashi Yoshitomi, Shinichi Nakamura
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Patent number: 6272306Abstract: A developing apparatus includes a developer bearing member for bearing and carrying developer to a developing area. A developer is borne on the developer bearing member, wherein the developer has a weight average particle size not exceeding 6.5 &mgr;m and contains an external additive of a charging polarity opposite to that of the developer. A voltage application device applies a voltage to the developer bearing member, wherein the voltage including at least a first voltage V1 for acting on the developer in a direction from the developer bearing member toward an image bearing member and a second voltage V2 for acting on the developer in a direction from an image bearing member toward said developer bearing member, and a charged potential VL of the image bearing member, a latent image potential VD a distance H between the developer bearing member and an image bearing member, and wherein the voltages V1 and V2 satisfy a following relationships: |V1−VL|/H≦3.Type: GrantFiled: October 13, 1999Date of Patent: August 7, 2001Assignee: Canon Kabushiki KaishaInventors: Masanobu Saito, Keiji Okano, Gaku Konishi, Yasushi Shimizu, Hiroshi Satoh, Akira Domon, Satoru Motohashi
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Patent number: 6240019Abstract: A non-volatile semiconductor memory device according to the invention comprises a memory cell array having a plurality of non-volatile memory cells, and a write state machine controlling a voltage applied to a memory cell selected from the memory cell array and a voltage application period, in accordance with each of reading of data from the selected memory cell, writing of data into the selected memory cell, and erasion of data from the selected memory. The write state machine executes writing, under a first writing condition, on a predetermined number of memory cells included in the memory cell array, and executes writing on memory cells other than the predetermined number of memory cells, under a second writing condition set in accordance with a result of the writing executed under the first writing condition.Type: GrantFiled: December 23, 1999Date of Patent: May 29, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Hitoshi Shiga, Toru Tanzawa, Masanobu Saito
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Patent number: 6229164Abstract: A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (TOX) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (Lg) of the electrode (2) is determined to be equal to or less than 0.3 &mgr;m; and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.5 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.Type: GrantFiled: November 16, 1999Date of Patent: May 8, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Hisayo Momose, Hiroshi Iwai, Masanobu Saito, Tatsuya Ohguro, Mizuki Ono, Takashi Yoshitomi, Shinichi Nakamura
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Patent number: 6217879Abstract: The present invention provides materials from laver (a seaweed) as the starting material, which are useful in the field of pharmaceutical preparation, the field of health food, etc. The present invention relates to enzyme-decomposed materials from laver comprising a peptide mixture having an antihypertensive action obtained by decomposing laver with pepsin, wherein laver is boiled as a starting material for 1 hour or more and then the broth is removed whereby their antihypertensive action is further raised while their bitter taste, smell, viscosity etc. are eliminated. Accordingly, these enzyme-decomposed materials are made further useful as an antihypertensive agent and also suitable when added to food for use as health food. Further, these materials after decomposed with pepsin are further decomposed with an enzyme having a peptidase activity thereby improving tastes and providing more suitable food additives.Type: GrantFiled: September 15, 1999Date of Patent: April 17, 2001Assignee: Shirako Co., Ltd.Inventors: Kunio Suetsuna, Masanobu Saito
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Patent number: 6167212Abstract: The present invention relates to a development density adjusting method in which development density is adjusted by varying ratio of application time of a voltage having the first voltage value to application time of a voltage having the second voltage value in one period, and difference between a potential of the developer bearing member and a potential of the electrostatic latent image, when the voltage having the first voltage value is applied to the developer bearing member.Type: GrantFiled: September 22, 1999Date of Patent: December 26, 2000Assignee: Canon Kabushiki KaishaInventors: Hiroshi Satoh, Keiji Okano, Masanobu Saito, Gaku Konishi, Yasushi Shimizu, Akira Domon, Satoru Motohashi
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Patent number: 6021929Abstract: A funnel shaped nozzle and a method for manufacturing the same, in which the nozzle is easily manufactured at a low cost, reduced in destabilization of a base material and has a high corrosion resistance. In carrying out the invention, a baked nozzle mainly composed of completely, or partially-stabilized zirconia, is impregnated with a solution that allows unstabilized zirconia to be precipitated or separated by heat. By heating the nozzle and coating an open surface of a component particle of base material with unstabilized zirconia, a nozzle reduced in destabilization of a base material and having a high corrosion resistance is obtained. As it is not required to produce a two-layered molding, production is facilitated, and a manufacturing cost is reduced, because a small amount of unstabilized zirconia is used.Type: GrantFiled: September 5, 1997Date of Patent: February 8, 2000Inventors: Masanobu Saito, Toshio Yamane, Seijiro Tanaka
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Patent number: 5990516Abstract: A semiconductor device comprises: a p-type semiconductor substrate (1); an insulating film (3); a gate electrode (2) formed on the substrate via the insulating film; and an n-type source/drain region (5) formed on both sides of a channel forming region (4) located under the gate electrode (2) formed on the substrate (1). In particular, the thickness (T.sub.OX) of the insulating film (3) is determined to be less than 2.5 nm at conversion rate of silicon oxide film (silicon oxide equivalent thickness); a gate length (L.sub.g) of the gate electrode (2) is determined to be equal to or less than 0.3 .mu.m; and further a voltage applied to the gate electrode (2) and the drain region (6) is determined to be 1.5 V or less. Therefore, in the MOSFET having the tunneling gate oxide film (3), the reliability of the transistor under the hot carrier stress can be improved, and the gate leakage current can be reduced markedly, so that the transistor characteristics can be improved markedly.Type: GrantFiled: September 13, 1995Date of Patent: November 23, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Hisayo Momose, Hiroshi Iwai, Masanobu Saito, Tatsuya Ohguro, Mizuki Ono, Takashi Yoshitomi, Shinichi Nakamura
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Patent number: 5955761Abstract: A semiconductor device capable of restraining a short channel effect and obtaining a current drivability that is as high as possible includes a semiconductor substrate, a gate insulating film formed on the surface of this substrate, a gate electrode formed on this gate insulating film and side wall insulating films formed on this gate electrode and along side walls of the gate insulating film. The semiconductor device further includes side wall conductor films formed adjacent to the side wall insulating films and a source/drain region formed in a surface region of the substrate under the side wall conductivity film and in a surface region, adjacent to the side wall conductivity film, of the semiconductor substrate. An impurity concentration in a depthwise direction of the substrate with the surface of the side wall conductor film serving as a starting point exhibits one maximum value in a predetermined depth but decreases in a portion deeper than the predetermined depth.Type: GrantFiled: April 30, 1998Date of Patent: September 21, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yoshitomi, Hiroshi Iwai, Masanobu Saito, Hisayo Momose, Tatsuya Ohguro, Mizuki Ono
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Patent number: 5903027Abstract: A MOS type semiconductor device has a gate whose length is 170 nm (0.17 .mu.m) or less, a junction depth of source and drain diffusion layers in the vicinity of a channel is 22 nm or less, and a concentration of impurities at the surface in the source and drain diffusion layers is made to 10.sup.20 cm.sup.-3 or more. Such structure is obtained using solid phase diffusion using heat range from 950.degree. C. to 1050.degree. C. and/or narrowing gate width by ashing or etching. The other MOS type semiconductor device is characterized in that the relationship between the junction depth x.sub.j ?nm! in the source and drain diffusion layer regions and the effective channel length L.sub.eff ?nm! is determined by L.sub.eff >0.69 x.sub.j -6.17.Type: GrantFiled: August 13, 1997Date of Patent: May 11, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yoshitomi, Masanobu Saito, Hisayo Momose, Hiroshi Iwai, Yukihiro Ushiku, Mizuki Ono, Yasushi Akasaka, Hideaki Nii, Satoshi Matsuda, Yasuhiro Katsumata, Tatsuya Ooguro, Claudio Fiegna
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Patent number: 5898203Abstract: A diffused server as a source and a drain. It is formed comprised of a deep first diffused layer and a shallow second diffused layer positioned between the first diffused layer and the channel region. In the second diffused region, a distribution in a depth direction of carriers has a profile in which the concentration is more than 5.times.10.sup.18 cm-.sup.-3 at the peak and is in correspondence with a carrier concentration of the semiconductor substrate at a depth less than 0.04 .mu.m. Since the second diffused layer has a high concentration, the short-channel effect can be suppressed. As the second diffused region, a solid phase diffusion source such as an impurity doped silicate glass is used.Type: GrantFiled: July 30, 1997Date of Patent: April 27, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yoshitomi, Masanobu Saito, Hisayo Momose, Hiroshi Iwai, Yukihiro Ushiku, Mizuki Ono, Yasushi Akasaka, Hideaki Nii, Satoshi Matsuda, Yasuhiro Katsumata
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Patent number: 5780901Abstract: A semiconductor device capable of restraining a short channel effect and obtaining a current drivability that is as high as possible includes a semiconductor substrate, a gate insulating film formed on the surface of this substrate, a gate electrode formed on this gate insulating film and side wall insulating films formed on this gate electrode and along side walls of the gate insulating film. The semiconductor device further includes side wall conductor films formed adjacent to the side wall insulating films and a source/drain region formed in a surface region of the substrate under the side wall conductivity film and in a surface region, adjacent to the side wall conductivity film, of the semiconductor substrate. An impurity concentration in a depthwise direction of the substrate with the surface of the side wall conductor film serving as a starting point exhibits one maximum value in a predetermined depth but decreases in a portion deeper than the predetermined depth.Type: GrantFiled: June 30, 1995Date of Patent: July 14, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yoshitomi, Hiroshi Iwai, Masanobu Saito, Hisayo Momose, Tatsuya Ohguro, Mizuki Ono
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Patent number: 5766965Abstract: A diffused layer serves as a source and a drain. It is formed comprised of a deep first diffused layer and a shallow second diffused layer positioned between the first diffused layer and the channel region. In the second diffused region, a distribution in a depth direction of carriers has a profile in which the concentration is more than 5.times.10.sup.18 cm.sup.-3 at the peak and is in correspondence with a carrier concentration of the semiconductor substrate at a depth less than 0.04 .mu.m. Since the second diffused layer has a high concentration, the short-channel effect can be suppressed. As the second diffused region, a solid phase diffusion source such as an impurity doped silicate glass is used.Type: GrantFiled: December 5, 1994Date of Patent: June 16, 1998Inventors: Takashi Yoshitomi, Masanobu Saito, Hisayo Momose, Hiroshi Iwai, Yukihiro Ushiku, Mizuki Ono, Yasushi Akasaka, Hideaki Nii, Satoshi Matsuda, Yasuhiro Katsumata
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Patent number: 5698881Abstract: A MOS type semiconductor device has a gate whose length is 170 nm (0.17 .mu.m) or less, a junction depth of source and drain diffusion layers in the vicinity of a channel is 22 nm or less, and a concentration of impurities at the surface in the source and drain diffusion layers is made to 10.sup.20 cm.sup.-3 or more. Such structure is obtained using solid phase diffusion using heat range from 950.degree. C. to 1050.degree. C. and/or narrowing gate width by ashing or etching. The other MOS type semiconductor device is characterized in that the relationship between the junction depth x.sub.j ?nm! in the source and drain diffusion layer regions and the effective channel length L.sub.eff ?nm! is determined by L.sub.eff >0.69 x.sub.j -6.17.Type: GrantFiled: December 2, 1994Date of Patent: December 16, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yoshitomi, Masanobu Saito, Hisayo Momose, Hiroshi Iwai, Yukihiro Ushiku, Mizuki Ono, Yasushi Akasaka, Hideaki Nii, Satoshi Matsuda, Yasuhiro Katsumata, Tatsuya Ooguro, Claudio Fiegna
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Patent number: 5669042Abstract: An image forming apparatus is provided for forming an image on a recording medium. The apparatus has a main body on which a process cartridge, which includes a frame, an image bearing member, a toner carrying member, and an attachment member for attaching the toner carrying member to the frame, is removably mountable. The apparatus also has a supporting device for supporting the process cartridge at the attachment member when the process cartridge is mounted in the apparatus and a feeding device for feeding the recording medium.Type: GrantFiled: March 17, 1994Date of Patent: September 16, 1997Assignee: Canon Kabushiki KaishaInventors: Kazunori Kobayashi, Kazumi Sekine, Tadayuki Tsuda, Isao Ikemoto, Kazushi Watanabe, Yoshikazu Sasago, Masanobu Saito, Shinya Noda
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Patent number: 5475472Abstract: An image forming apparatus includes an image bearing member; a charging member for charging the image bearing member; an image forming device for forming an image on the image bearing member; and an impedance circuit between the charging member and a voltage source for supplying electric power to the charging member, the impedance circuit having an impedance which is peculiar to individual image forming apparatus in accordance with an impedance of the charging member.Type: GrantFiled: March 16, 1994Date of Patent: December 12, 1995Assignee: Canon Kabushiki KaishaInventors: Masanobu Saito, Masaharu Ohkubo
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Patent number: 5434440Abstract: A diffused layer serves as a source and a drain. It is formed comprised of a deep first diffused layer and a shallow second diffused layer positioned between the first diffused layer and the channel region. In the second diffused region, a distribution in a depth direction of carriers has a profile in which the concentration is more than 5.times.10.sup.18 cm.sup.-3 at the peak and is in correspondence with a carrier concentration of the semiconductor substrate at a depth less than 0.04 .mu.m. Since the second diffused layer has a high concentration, the short-channel effect can be suppressed. As the second diffused region, a solid phase diffusion source such as an impurity doped silicate glass is used.Type: GrantFiled: May 28, 1993Date of Patent: July 18, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yoshitomi, Masanobu Saito, Hisayo Momose, Hiroshi Iwai, Yukihiro Ushiku, Mizuki Ono, Yasushi Akasaka, Hideaki Nii, Satoshi Matsuda, Yasuhiro Katsumata
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Patent number: 5420671Abstract: A charging device contactable to a member in order to charge it electrically. The voltage of the charging member includes an AC component. A controller controls the AC component so as to be a constant current, by which the member to be charged can be stably and uniformly charged even if ambient conditions change.Type: GrantFiled: February 15, 1994Date of Patent: May 30, 1995Assignee: Canon Kabushiki KaishaInventors: Hiroki Kisu, Toshio Miyamoto, Yohji Tomoyuki, Junji Araya, Shunji Nakamura, Masanobu Saito
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Patent number: 5253024Abstract: The present invention relates to a fixing apparatus having a pair of rotary members for pinching and conveying a supporting material bearing a non-fixed toner image thereon, thereby fixing the non-fixed toner image on the supporting material and wherein a rectifier element is connected to at least one of the rotary members in a predetermined orientation, whereby the present invention prevent a toner offset that the toner on the supporting material is adhered to the rotary members.Type: GrantFiled: December 10, 1991Date of Patent: October 12, 1993Assignee: Canon Kabushiki KaishaInventors: Koichi Okuda, Yoji Tomoyuki, Toshio Miyamoto, Junji Araya, Yukihiro Ohzeki, Masanobu Saito, Shunji Nakamura, Yasumasa Ohtsuka, Tatsunori Ishiyama, Katsuhiko Nishimura, Akira Hayakawa, Yasushi Sato, Kimio Nakahata
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Patent number: 5132738Abstract: An image forming apparatus includes a movable image bearing member, a charger for electrically charging the image bearing member, latent image forming device for forming a latent image with use of the charger, a developing device for developing the latent image formed by the latent image forming device with toner electrically charged to a polarity the same as a polarity to which the image bearing member is charged by the charger, image transfer member contactable to a back side of a transfer material to transfer a toner image provided by the developing device from the image bearing member to the transfer material, a voltage application device for applying a voltage to the transfer member, the voltage application device applying a voltage having a polarity the same as that of the toner to the transfer member during non-transferring operation, and a device for providing different potentials for a portion of the image bearing member to be opposed to the image transfer device during the non-transfer action by saiType: GrantFiled: November 8, 1991Date of Patent: July 21, 1992Assignee: Canon Kabushiki KaishaInventors: Shunji Nakamura, Hiroki Kisu, Yohji Tomoyuki, Masanobu Saito, Junji Araya, Toshio Miyamoto