Abstract: A three-dimensional memory device includes a first-tier structure located over a substrate and including a first alternating stack of first insulating layers and first electrically conductive layers. a second-tier structure located over the first-tier structure and including a second alternating stack of second insulating layers and second electrically conductive layers, memory stack structures vertically extending through the first alternating stack and the second alternating stack, primary support pillar structures, and auxiliary support pillar structures vertically extending through the first alternating stack, underlying the second stepped surfaces, and located below a horizontal plane including a bottommost surface of the second alternating stack.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, a perforated dielectric moat structure vertically extending through the alternating stack, and an interconnection via structure laterally surrounded by the perforated dielectric moat structure and vertically extending through each insulating layer within the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of memory elements located at levels of the electrically conductive layers. The perforated dielectric moat structure includes a plurality of lateral openings at each level of the insulating layers, and does not include any opening at levels of the electrically conductive layers.

Abstract: A three-dimensional memory device includes a first-tier structure located over a substrate and including a first alternating stack of first insulating layers and first electrically conductive layers. a second-tier structure located over the first-tier structure and including a second alternating stack of second insulating layers and second electrically conductive layers, memory stack structures vertically extending through the first alternating stack and the second alternating stack, primary support pillar structures, and auxiliary support pillar structures vertically extending through the first alternating stack, underlying the second stepped surfaces, and located below a horizontal plane including a bottommost surface of the second alternating stack.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, a perforated dielectric moat structure vertically extending through the alternating stack, and an interconnection via structure laterally surrounded by the perforated dielectric moat structure and vertically extending through each insulating layer within the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of memory elements located at levels of the electrically conductive layers. The perforated dielectric moat structure includes a plurality of lateral openings at each level of the insulating layers, and does not include any opening at levels of the electrically conductive layers.

Abstract: An alternating layer stack of insulating layers and sacrificial material layers is formed over a semiconductor substrate, and memory stack structures are formed through the vertically-alternating layer stack. A pair of unconnected barrier trenches or a moat trench is formed through the alternating stack concurrently with formation of backside trenches. Backside recesses are formed by isotropically etching the sacrificial material layers selective to the insulating layers while a dielectric liner covers the barrier trenches or the moat trench. A vertically alternating sequence of the insulating plates and the dielectric spacer plates is provided between the pair of barrier trenches or inside the moat trench. Electrically conductive layers are formed in the backside recesses. A first conductive via structure is formed through the vertically alternating sequence concurrently with formation of a second conductive via structure through a dielectric material portion adjacent to the alternating stack.

Abstract: An alternating layer stack of insulating layers and sacrificial material layers is formed over a semiconductor substrate, and memory stack structures are formed through the vertically-alternating layer stack. A pair of unconnected barrier trenches or a moat trench is formed through the alternating stack concurrently with formation of backside trenches. Backside recesses are formed by isotropically etching the sacrificial material layers selective to the insulating layers while a dielectric liner covers the barrier trenches or the moat trench. A vertically alternating sequence of the insulating plates and the dielectric spacer plates is provided between the pair of barrier trenches or inside the moat trench. Electrically conductive layers are formed in the backside recesses. A first conductive via structure is formed through the vertically alternating sequence concurrently with formation of a second conductive via structure through a dielectric material portion adjacent to the alternating stack.

Abstract: A lower source layer, a sacrificial source-level material layer, and an upper source layer are formed over a substrate. The lower source layer includes a recess trench in which a recessed surface of the lower source layer is vertically recessed relative to a topmost surface of the lower source layer. An alternating stack of insulating layers and spacer material layers is subsequently formed. Memory stack structures are formed through the alternating stack. A backside trench is formed through the alternating stack such that a bottom surface of the backside trench is formed within an area of the recess trench in a thickened portion of the sacrificial source-level material layer. The sacrificial source-level material layer is replaced with a source contact layer.

Abstract: Memory openings and support openings can be formed through an alternating stack of insulating layers and sacrificial material layers. A set of dielectric layers and at least one semiconductor material layer can be sequentially deposited in each of the memory openings and the support openings. The at least one semiconductor material layer is removed from inside the support openings, while the at least one semiconductor material layer is not removed from inside the memory openings. Memory stack structures and support pillar structures are formed in the memory openings and the support openings, respectively. The sacrificial material layers are replaced with electrically conductive layers. Removal of the at least one semiconductor material layer from the support pillar structures reduces or eliminates leakage current through the support pillar structures.

Abstract: Memory openings and support openings can be formed through an alternating stack of insulating layers and sacrificial material layers. A set of dielectric layers and at least one semiconductor material layer can be sequentially deposited in each of the memory openings and the support openings. The at least one semiconductor material layer is removed from inside the support openings, while the at least one semiconductor material layer is not removed from inside the memory openings. Memory stack structures and support pillar structures are formed in the memory openings and the support openings, respectively. The sacrificial material layers are replaced with electrically conductive layers. Removal of the at least one semiconductor material layer from the support pillar structures reduces or eliminates leakage current through the support pillar structures.

Abstract: A method of making a monolithic three dimensional NAND string includes forming a select gate layer of a third material over a major surface of a substrate, forming a stack of alternating first material and second material layers over the select gate layer, where the first material, the second material and the third material are different from each other, and etching the stack using a first etch chemistry to form at least one opening in the stack at least to the select gate layer, such that the select gate layer acts as an etch stop layer during the step of etching.

Abstract: A dielectric liner, a bottom conductive layer, and a stack of alternating layers including insulator layers and spacer material layers are sequentially formed over a substrate. A memory opening extending through the stack can be formed by an anisotropic etch process that employs the bottom conductive layer as an etch stop layer. The memory opening is extended downward by etching through the bottom conductive layer and the dielectric liner, while minimizing an overetch into the substrate. A memory stack structure can be formed in the memory opening. Subsequently, a backside contact trench can be formed through the stack employing the bottom conductive layer as an etch stop layer. The spacer material layers can be removed to form backside recesses, which are filled with a conductive material to form electrically conductive layers. The remaining portion of the bottom conductive layer can be employed as a source select gate electrode.

Abstract: A dielectric liner, a bottom conductive layer, and a stack of alternating layers including insulator layers and spacer material layers are sequentially formed over a substrate. A memory opening extending through the stack can be formed by an anisotropic etch process that employs the bottom conductive layer as an etch stop layer. The memory opening is extended downward by etching through the bottom conductive layer and the dielectric liner, while minimizing an overetch into the substrate. A memory stack structure can be formed in the memory opening. Subsequently, a backside contact trench can be formed through the stack employing the bottom conductive layer as an etch stop layer. The spacer material layers can be removed to form backside recesses, which are filled with a conductive material to form electrically conductive layers. The remaining portion of the bottom conductive layer can be employed as a source select gate electrode.

Abstract: A method of making a semiconductor device including forming a sacrificial feature over a substrate, forming a plurality of etch through regions having an etch through material and an etch stop region having an etch stop material over the sacrificial feature, forming a stack of alternating layers of a first material and a second material over the plurality of the etch through regions and the plurality of the etch stop regions, etching the stack to form a plurality of openings through the stack and through the etch through regions to expose the sacrificial feature, such that the etch through material is etched preferentially compared to the first and the second materials of the stack, removing the sacrificial feature through the plurality of openings and etching the stack to form a slit trench up to or only partially through the etch stop region, such that the first and the second materials of the stack are etched preferentially compared to the etch stop material.

Abstract: A method of making a monolithic three dimensional NAND string includes forming a select gate layer of a third material over a major surface of a substrate, forming a stack of alternating first material and second material layers over the select gate layer, where the first material, the second material and the third material are different from each other, and etching the stack using a first etch chemistry to form at least one opening in the stack at least to the select gate layer, such that the select gate layer acts as an etch stop layer during the step of etching.

Abstract: A semiconductor device production method includes: forming a protection film on a semiconductor substrate; forming a first resist pattern on the protection film; implanting a first impurity ion into the semiconductor substrate using the first resist pattern as a mask; removing the first resist pattern; forming on the surface of the semiconductor substrate a chemical reaction layer that takes in surface atoms from the semiconductor substrate through chemical reaction, after the removing of the first resist pattern; removing the chemical reaction layer formed on the semiconductor substrate and removing the surface of the semiconductor substrate, after the forming of the chemical reaction layer; and growing a semiconductor layer epitaxially on the surface of the semiconductor substrate, after the removing of the surface of the semiconductor substrate.

Abstract: A stack can be patterned by a first etch process to form an opening defining sidewall surfaces of a patterned material stack. A masking layer can be non-conformally deposited on sidewalls of an upper portion of the patterned material stack, while not being deposited on sidewalls of a lower portion of the patterned material stack. The sidewalls of a lower portion of the opening can be laterally recessed employing a second etch process, which can include an isotropic etch component. The sidewalls of the upper portion of the opening can protrude inward toward the opening to form an overhang over the sidewalls of the lower portion of the opening. The overhang can be employed to form useful structures such as an negative offset profile in a floating gate device or vertically aligned control gate electrodes for vertical memory devices.

Abstract: A method of making a semiconductor device includes forming a stack of alternating layers of a first material and a second material over a substrate, etching the stack to form at least one opening extending partially through the stack and forming a masking layer on a sidewall and bottom surface of the at least one opening. The method also includes removing the masking layer from the bottom surface of the at least one opening while leaving the masking layer on the sidewall of the at least one opening, and further etching the at least one opening to extend the at least one opening further through the stack while the masking layer remains on the sidewall of the at least one opening.

Abstract: A method of making a semiconductor device including forming a sacrificial feature over a substrate, forming a plurality of etch through regions having an etch through material and an etch stop region having an etch stop material over the sacrificial feature, forming a stack of alternating layers of a first material and a second material over the plurality of the etch through regions and the plurality of the etch stop regions, etching the stack to form a plurality of openings through the stack and through the etch through regions to expose the sacrificial feature, such that the etch through material is etched preferentially compared to the first and the second materials of the stack, removing the sacrificial feature through the plurality of openings and etching the stack to form a slit trench up to or only partially through the etch stop region, such that the first and the second materials of the stack are etched preferentially compared to the etch stop material.

Abstract: A stack can be patterned by a first etch process to form an opening defining sidewall surfaces of a patterned material stack. A masking layer can be non-conformally deposited on sidewalls of an upper portion of the patterned material stack, while not being deposited on sidewalls of a lower portion of the patterned material stack. The sidewalls of a lower portion of the opening can be laterally recessed employing a second etch process, which can include an isotropic etch component. The sidewalls of the upper portion of the opening can protrude inward toward the opening to form an overhang over the sidewalls of the lower portion of the opening. The overhang can be employed to form useful structures such as an negative offset profile in a floating gate device or vertically aligned control gate electrodes for vertical memory devices.

Abstract: A method of making a semiconductor device includes forming a stack of alternating layers of a first material and a second material over a substrate, etching the stack to form at least one opening extending partially through the stack and forming a masking layer on a sidewall and bottom surface of the at least one opening. The method also includes removing the masking layer from the bottom surface of the at least one opening while leaving the masking layer on the sidewall of the at least one opening, and further etching the at least one opening to extend the at least one opening further through the stack while the masking layer remains on the sidewall of the at least one opening.