Patents by Inventor Masanori Terahara

Masanori Terahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7601576
    Abstract: The method for fabricating a semiconductor device comprises the steps of: forming on a silicon substrate 10 a hard mask 20 of a silicon oxide film 12, and a silicon nitride film 14 having a width smaller than a width of the silicon oxide film 12; etching the silicon substrate 10 with the hard mask 20 as the mask to form a trench 26 for defining an active region 24 in the silicon substrate 10; and forming a silicon oxide film 28 on the silicon substrate 10 with the trench 26 formed in.
    Type: Grant
    Filed: November 28, 2005
    Date of Patent: October 13, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Rintaro Suzuki, Hiroshi Morioka, Masanori Terahara
  • Publication number: 20090197355
    Abstract: A method for manufacturing a semiconductor device that controls the influence of a thickness of a stopper film even if there is a change in the thickness of the stopper film by measuring the thickness prior to etching to a predetermined thickness.
    Type: Application
    Filed: February 3, 2009
    Publication date: August 6, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventor: Masanori Terahara
  • Patent number: 7541120
    Abstract: After forming a resist film on a Si substrate, a circuit pattern for a semiconductor integrated circuit, a first L-shaped length measuring pattern and a cross-shaped monitor pattern for alignment are formed on the resist film. Next, based on these patterns, the Si substrate is patterned. Thereafter, a polysilicon film is formed above the Si substrate. Subsequently, a resist film is formed on the polysilicon film. Next, a circuit pattern for a semiconductor integrated circuit, a second L-shaped length measuring pattern and a cross-shaped monitor pattern for alignment are formed on the resist film. At this time, the second L-shaped length measuring pattern is made to face in a direction in which the first L-shaped length measuring pattern is rotated 180 degrees in plane view. By patterning the polysilicon film with these patterns as a mask, a gate electrode is formed.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: June 2, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventor: Masanori Terahara
  • Patent number: 7501686
    Abstract: A semiconductor device is disclosed that includes a semiconductor substrate, a device region disposed at a predetermined location of the semiconductor substrate, and a shallow trench isolation region that isolates the device region. The shallow trench isolation region includes a trench, a nitride film liner disposed at an upper portion of a side wall of the trench, and a thermal oxide film disposed at a lower portion of the side wall of the trench. The shallow trench isolation is arranged such that the width of a second portion of the shallow trench isolation region at which the thermal oxide film is disposed may be wider than the width of a first portion of the shallow trench isolation region at which the lower end of the nitride film liner is disposed.
    Type: Grant
    Filed: February 22, 2006
    Date of Patent: March 10, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Masaki Okuno, Sadahiro Kishii, Hiroshi Morioka, Masanori Terahara, Shigeo Satoh, Kaina Suzuki
  • Publication number: 20080241973
    Abstract: The method of manufacturing a semiconductor device has deciding an amount of a correction of a mask pattern for a size of an active region of a semiconductor substrate, correcting the mask pattern on the basis of the decided amount of the correction, and exposing a resist film by using an exposure mask having the corrected mask pattern.
    Type: Application
    Filed: March 21, 2008
    Publication date: October 2, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Masanori TERAHARA
  • Publication number: 20080237784
    Abstract: A semiconductor device formed in a semiconductor substrate wherein the semiconductor substrate has a trench for isolating elements from each other, the trench has unevenness at the bottom thereof, and an insulator is buried in the trench.
    Type: Application
    Filed: April 2, 2008
    Publication date: October 2, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Masato MIYAMOTO, Masanori TERAHARA
  • Publication number: 20080237812
    Abstract: A method of manufacturing a semiconductor device includes the steps of forming a trench on a semiconductor substrate to define a first and a second element regions; burying a first oxide film in the trench; forming a second oxide film on surfaces of the first and second element regions; performing a first ion doping using a first mask which is exposing a first region containing the first element region and a part of the first oxide; performing a second ion doping using a second mask which is exposing a second region containing the second element region and a part of the first oxide film; and removing the second oxide film formed in the first element region and the second element region by etching, and the first oxide film is selectively thinned using the first or second mask after performing the first or second ion doping.
    Type: Application
    Filed: March 21, 2008
    Publication date: October 2, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Masanori TERAHARA, Masaki NAKAGAWA
  • Publication number: 20080081384
    Abstract: A semiconductor device fabrication method is disclosed. The method comprises an insulating film forming step of forming an insulating film on a semiconductor substrate; a trench forming step of forming a trench for device isolation in a predetermined part of the semiconductor substrate; a trench filling step of forming a buried oxide film filling the trench; a polishing step of polishing the buried oxide film on the semiconductor substrate until the insulating film is exposed; a thickness measuring step of measuring the thickness of the insulating film remaining after the polishing; an etching amount determining step of determining an etching amount of etching the polished buried oxide film based on the measured thickness of the remaining insulating film; and a buried oxide film etching step of etching the polished buried oxide film based on the determined etching amount.
    Type: Application
    Filed: August 27, 2007
    Publication date: April 3, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Junji OH, Masanori TERAHARA
  • Publication number: 20070228488
    Abstract: A trench is formed in the surface layer of a semiconductor substrate, surrounding an active region. A lower insulating film made of insulating material fills a lower region of the trench. An upper insulating film fills a region of the trench above the lower insulating film. The upper insulating film has therein a stress generating tensile strain in a surface layer of the active region.
    Type: Application
    Filed: October 3, 2006
    Publication date: October 4, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Sadahiro Kishii, Hirofumi Watatani, Masanori Terahara, Ryo Tanabe, Kaina Suzuki, Shigeo Satoh
  • Publication number: 20070048916
    Abstract: The method for fabricating a semiconductor device comprises the steps of: forming on a silicon substrate 10 a hard mask 20 of a silicon oxide film 12, and a silicon nitride film 14 having a width smaller than a width of the silicon oxide film 12; etching the silicon substrate 10 with the hard mask 20 as the mask to form a trench 26 for defining an active region 24 in the silicon substrate 10; and forming a silicon oxide film 28 on the silicon substrate 10 with the trench 26 formed in.
    Type: Application
    Filed: November 28, 2005
    Publication date: March 1, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Rintaro Suzuki, Hiroshi Morioka, Masanori Terahara
  • Publication number: 20060281245
    Abstract: A semiconductor device is disclosed that includes a semiconductor substrate, a device region disposed at a predetermined location of the semiconductor substrate, and a shallow trench isolation region that isolates the device region. The shallow trench isolation region includes a trench, a nitride film liner disposed at an upper portion of a side wall of the trench, and a thermal oxide film disposed at a lower portion of the side wall of the trench. The shallow trench isolation is arranged such that the width of a second portion of the shallow trench isolation region at which the thermal oxide film is disposed may be wider than the width of a first portion of the shallow trench isolation region at which the lower end of the nitride film liner is disposed.
    Type: Application
    Filed: February 22, 2006
    Publication date: December 14, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Masaki Okuno, Sadahiro Kishii, Hiroshi Morioka, Masanori Terahara, Shigeo Satoh, Kaina Suzuki
  • Publication number: 20060093963
    Abstract: After forming a resist film on a Si substrate, a circuit pattern for a semiconductor integrated circuit, a first L-shaped length measuring pattern and a cross-shaped monitor pattern for alignment are formed on the resist film. Next, based on these patterns, the Si substrate is patterned. Thereafter, a polysilicon film is formed above the Si substrate. Subsequently, a resist film is formed on the polysilicon film. Next, a circuit pattern for a semiconductor integrated circuit, a second L-shaped length measuring pattern and a cross-shaped monitor pattern for alignment are formed on the resist film. At this time, the second L-shaped length measuring pattern is made to face in a direction in which the first L-shaped length measuring pattern is rotated 180 degrees in plane view. By patterning the polysilicon film with these patterns as a mask, a gate electrode is formed.
    Type: Application
    Filed: February 28, 2005
    Publication date: May 4, 2006
    Applicant: FUJITSU LIMITED
    Inventor: Masanori Terahara
  • Patent number: 6979610
    Abstract: The semiconductor device fabrication method comprises the step of forming a first insulation film 14 over a semiconductor substrate 10; the step of forming a semiconductor film 16 over the first insulation film 14; the step of forming a resist film 20 over the semiconductor film 16; the step of forming openings 21 in the resist film 20; the step of etching the semiconductor film 16 with the resist film 20 as the mask; the step of etching the first insulation film 14 with the semiconductor film 16 as the mask; and the step of etching the semiconductor substrate 10 with the first insulation film 14 as the mask to form trenches 22 in the semiconductor substrate 10. Silicon nitride film is patterned, using a mask of polysilicon film, whereby the silicon nitride film can be etched with high selectivity to the polysilicon film. Accordingly, a good pattern of the silicon nitride film can be formed.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: December 27, 2005
    Assignee: Fujitsu Limited
    Inventors: Masanori Terahara, Hiroshi Morioka
  • Publication number: 20040092082
    Abstract: The semiconductor device fabrication method comprises the step of forming a first insulation film 14 over a semiconductor substrate 10; the step of forming a semiconductor film 16 over the first insulation film 14; the step of forming a resist film 20 over the semiconductor film 16; the step of forming openings 21 in the resist film 20; the step of etching the semiconductor film 16 with the resist film 20 as the mask; the step of etching the first insulation film 14 with the semiconductor film 16 as the mask; and the step of etching the semiconductor substrate 10 with the first insulation film 14 as the mask to form trenches 22 in the semiconductor substrate 10. Silicon nitride film is patterned, using a mask of polysilicon film, whereby the silicon nitride film can be etched with high selectivity to the polysilicon film. Accordingly, a good pattern of the silicon nitride film can be formed.
    Type: Application
    Filed: October 29, 2003
    Publication date: May 13, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Masanori Terahara, Hiroshi Morioka