Abstract: Mitigating electrostatic discharge damage when fabricating a 3-D integrated circuit package, wherein in one embodiment when a second tier die is placed in contact with a first tier die, conductive bumps near the perimeter of the second tier die that are electrically coupled to the substrate of the second tier die make contact with corresponding conductive bumps on the first tier die that are electrically coupled to the substrate of first tier die before other signal conductive bumps and power conductive bumps on the second tier and first tier dice make electrical contact.

Abstract: A semiconductor die includes a semiconductive substrate layer with first and second sides, a metal layer adjacent the second side of the semiconductive substrate layer, one or more active devices in an active layer on the first side of the semiconductive substrate layer; and a passive device in the metal layer in electrical communication with the active layer. The passive device can electrically couple to the active layer with through silicon vias (TSVs).

Abstract: A method for manufacturing a semiconductor device includes fabricating an active layer on a first side of a semiconductor substrate. The method also includes fabricating a metal layer on a second side of the semiconductor substrate. The metal layer includes a passive device embedded within the metal layer. The passive device can electrically couple to the active layer with through vias.

Abstract: An electrical component includes an inkjet-printed graphene electrode. Graphene oxide flakes are deposited on a substrate in a graphene oxide ink using an inkjet printer. The deposited graphene oxide is thermally reduced to graphene. The electrical properties of the electrode are comparable to those of electrodes made using activated carbon, carbon nanotubes or graphene made by other methods. The electrical properties of the graphene electrodes may be tailored by adding nanoparticles of other materials to the ink to serve as conductivity enhancers, spacers, or to confer pseudocapacitance. Inkjet-printing can be used to make graphene electrodes of a desired thickness in preselected patterns. Inkjet printing can be used to make highly-transparent graphene electrodes. Inkjet-printed graphene electrodes may be used to fabricate double-layer capacitors that store energy by nanoscale charge separation at the electrode-electrolyte interface (i.e., “supercapacitors”).

Abstract: A three dimensional on-chip inductor, transformer and radio frequency amplifier are disclosed. The radio frequency amplifier includes a pair of transformers and a transistor. The transformers include at least two inductively coupled inductors. The inductors include a plurality of segments of a first metal layer, a plurality of segments of a second metal layer, a first inductor input, a second inductor input, and a plurality of through silicon vias coupling the plurality of segments of the first metal layer and the plurality of segments of the second metal layer to form a continuous, non-intersecting path between the first inductor input and the second inductor input. The inductors can have a symmetric or asymmetric geometry. The first metal layer can be a metal layer in the back-end-of-line section of the chip. The second metal layer can be located in the redistributed design layer of the chip.

Abstract: A three dimensional on-chip radio frequency amplifier is disclosed that includes first and second transformers and a first transistor. The first transformer includes first and second inductively coupled inductors. The second transformer includes third and fourth inductively coupled inductors. Each inductor includes multiple first segments in a first metal layer; multiple second segments in a second metal layer; first and second inputs, and multiple through vias coupling the first and second segments to form a continuous path between the first and second inputs. The first input of the first inductor is coupled to an amplifier input; the first input of the second inductor is coupled to the first transistor gate; the first input of the third inductor is coupled to the first transistor drain, the first input of the fourth inductor is coupled to an amplifier output. The second inductor inputs and the first transistor source are coupled to ground.

Abstract: A method for manufacturing a semiconductor device includes fabricating an active layer on a first side of a semiconductor substrate. The method also includes fabricating a metal layer on a second side of the semiconductor substrate. The metal layer includes a passive device embedded within the metal layer. The passive device can electrically couple to the active layer with through vias.

Abstract: A semiconductor die includes a semiconductive substrate layer with first and second sides, a metal layer adjacent the second side of the semiconductive substrate layer, one or more active devices in an active layer on the first side of the semiconductive substrate layer; and a passive device in the metal layer in electrical communication with the active layer. The passive device can electrically couple to the active layer with through silicon vias (TSVs).

Abstract: A semiconductor die includes a semiconductive substrate layer with first and second sides, a metal layer adjacent the second side of the semiconductive substrate layer, one or more active devices in an active layer on the first side of the semiconductive substrate layer; and a passive device in the metal layer in electrical communication with the active layer. The passive device can electrically couple to the active layer with through silicon vias (TSVs).

Abstract: Mitigating electrostatic discharge damage when fabricating a 3-D integrated circuit package, wherein in one embodiment when a second tier die is placed in contact with a first tier die, conductive bumps near the perimeter of the second tier die that are electrically coupled to the substrate of the second tier die make contact with corresponding conductive bumps on the first tier die that are electrically coupled to the substrate of first tier die before other signal conductive bumps and power conductive bumps on the second tier and first tier dice make electrical contact.

Abstract: An electronic seal (100), housing (1) for a transponder (200), which may form part of an electronic seal (100) and a transponder device is provided. The electronic seal (100) has a sealing mechanism (5). A transponder receptacle (50), and an actuator (4) are provided by or with the housing (1). The actuator (4) is actuated upon engagement of the sealing mechanism (5) to render the transponder (200) operable. The transponder receptacle (50) may hold the transponder (200) so as to extend into three planes.

Abstract: An interconnect sensor for detecting delamination due to coefficient of thermal expansion mismatch and/or mechanical stress. The sensor comprises a conductive path that includes a via disposed between two back end of line metal layers separated by a dielectric. The via is coupled between a first probe structure and a second probe structure and mechanically coupled to a stress inducing structure. The via is configured to alter the conductive path in response to mechanical stress caused by the stress inducing structure. The stress inducing structure can be a through silicon via or a solder ball. The dielectric material can be a low-k dielectric material. In another embodiment, a method of forming an interconnect sensor is provided for detecting delamination.

Abstract: A three dimensional on-chip inductor, transformer and radio frequency amplifier are disclosed. The radio frequency amplifier includes a pair of transformers and a transistor. The transformers include at least two inductively coupled inductors. The inductors include a plurality of segments of a first metal layer, a plurality of segments of a second metal layer, a first inductor input, a second inductor input, and a plurality of through silicon vias coupling the plurality of segments of the first metal layer and the plurality of segments of the second metal layer to form a continuous, non-intersecting path between the first inductor input and the second inductor input. The inductors can have a symmetric or asymmetric geometry. The first metal layer can be a metal layer in the back-end-of-line section of the chip. The second metal layer can be located in the redistributed design layer of the chip.

Abstract: An electronic seal (300) is described. The seal includes a sealing mechanism (301, 302) for sealing a value item and a cover (304), which inhibits access to the sealing mechanism (301, 302). A trigger (303) is held in a substantially fixed relationship relative to the sealing mechanism (301, 302) when the cover (304) is moved away from the sealing mechanism (301, 302). The trigger (303) holds in position a tensioned spring (305), which is released when the cover (304) is moved away from the sealing mechanism (301, 302). The released spring (107) then impacts part of a transponder (201) in the electronic seal (300).

Abstract: A circuit for recording a magnitude of an ESD event during semiconductor assembly includes a voltage divider connected between an input and a ground. The circuit also includes a measurement block having a recorder device. Each measurement block receives current from a segment of the voltage divider. The magnitude of the ESD event is determined based upon a read-out of the measurement devices after the ESD event. The recorder device may be a capacitor that would be damaged during the ESD event. During the ESD event the capacitor may be damaged. Reading out the recorder device determines if the magnitude of the ESD event exceeded a threshold magnitude that damages the capacitor.

Abstract: An integrated magnetic film enhanced inductor and a method of forming an integrated magnetic film enhanced inductor are disclosed. The integrated magnetic film enhanced inductor includes an inductor metal having a first portion and a second portion, a top metal or bottom metal coupled to the inductor metal, and an isolation film disposed one of in, on, and adjacent to at least one of the first portion and the second portion of the inductor metal. The isolation film includes a magnetic material, such as a magnetic film.

Abstract: A semiconductor die includes a semiconductive substrate layer with first and second sides, a metal layer adjacent the second side of the semiconductive substrate layer, one or more active devices in an active layer on the first side of the semiconductive substrate layer; and a passive device in the metal layer in electrical communication with the active layer. The passive device can electrically couple to the active layer with through silicon vias (TSVs).

Abstract: An electronic seal (100), housing (1) for a transponder (200), which may form part of an electronic seal (100) and a transponder device is provided. The electronic seal (100) has a sealing mechanism (5). A transponder receptacle (50), and an actuator (4) are provided by or with the housing (1). The actuator (4) is actuated upon engagement of the sealing mechanism (5) to render the transponder (200) operable. The transponder receptacle (50) may hold the transponder (200) so as to extend into three planes.

Abstract: A container 11, carries a component 12 of the telemetry system. The container mounted unit 12 transmits via its antenna 34, a signal 41 containing data indicating the status of the container. This signal is received by shipboard transponder 32 including an antenna 33, a first transceiver 35 for communication with shipboard devices such as the container module 12, control unit 36 which monitors and buffers signals for re-transmission and routes incoming signals, and a second transceiver 37 which transmits and receives signals 39, to and from the satellite 15 via its antenna 38. Thus signals from the container mounted module 12 may be relayed via the shipboard relay 32, the satellite 17 and the communications network 19, 20, 21 to the receiver station 22.