Abstract: A host device is coupled to a peripheral device such as a multi media card or the like, where the peripheral device includes a solid state data storage segment. The peripheral device has means for initiating a defragmentation function, such as registers for comparing a current performance measure against a threshold performance metric, or block validity parameters received form the host device for the data storage segment of the peripheral device. Once met, the means for initiating cause a defragmentation function to execute on the data storage segment. A logical layer of the data storage segment is accessed by the host device and a physical layer of the data storage segment is accessed by the peripheral device. The defragmentation program may be resident on either the host or peripheral device. Defragmentation may be enabled to execute automatically once initiated, such as by a continuous or periodic background scan of current performance of the data storage segment.

Abstract: Accessing data stored in a memory device through an interface, with addressing data on the memory device through at least one address bus, controlling at least data flow to and from the memory device through at least one command bus, and transferring data to and from the memory through at least one data bus wherein commands on the command bus are adjusted depending on the type of memory connected to the interface.

Abstract: The invention relates to a memory unit with at least two memory areas for storing data, first terminals for accessing data within the memory areas, and second terminals for accessing data within the memory areas. To provide multi-purpose access to the memory, the memory unit provides at least two access control means for providing selectively sole addressing and accessing data through one of the terminals, or individual addressing and accessing data through each of the terminals, respectively.

Abstract: A mode indexing table is used for listing the available modes in a multimode device. From information in the mode indexing table, a host recognizes the modes as listed in the table. The host has a mandatory initialization mode using a known technique, such that the device can enter into an initialization mode directly or via a boot function. During initialization, the host receives the remaining part of the table from the multi-mode device and recognizes the functionality of each of the listed modes in the table. Among the available modes, some modes are allowed to access data of other modes according to the level of access. The multimode device has some commands that can be used for direct mode switching.

Abstract: A method and apparatus for addressing a plurality of mass memory components coupled to a host device. The memory components can be arranged in a chain or in a ring configuration. In a ring, each memory component receives a bit pattern from the preceding stage and sends a bit pattern to the next stage in consecutive clock periods. Based on the received bit pattern, a recipient component knows the bus width between itself and the sending component. In a chain, each memory component also sends the received bit pattern back to the preceding stage. The memory component can generate its own address by counting clock periods. Alternatively, a recipient component changes its received bit pattern before sending the bit pattern to the next stage. As such, the recipient component knows its address based on the received bit pattern.

Abstract: The present invention relates to a method for connecting a memory component to an electronic device by a connection bus. At least a first interface protocol and a second interface protocol are available on the connection bus, wherein the memory component is recognized. On the basis of the recognition, it is determined, if the first interface protocol or said second interface protocol are available in the memory component, wherein on the basis of the recognition, one of the protocols available in the memory component is selected for use on the connection bus. The invention also relates to a system, in which the method is applied, as well as an electronic device, and a bus connection.

Abstract: Accessing data stored in a memory device through an interface, with addressing data on the memory device through at least one address bus, controlling at least data flow to and from the memory device through at least one command bus, and transferring data to and from the memory through at least one data bus wherein commands on the command bus are adjusted depending on the type of memory connected to the interface.

Abstract: A method, mobile device, system, and software are devised in order to implement a write method that includes two different types of write commands, depending upon the length of a data burst to memory. A first write command is provided for a first type of burst and/or a second write command is provided for a second type of burst. The first type of burst is a burst of substantially a certain length. The second type of burst has length that is substantially an integer multiple of the length of the first type of burst, such as two or four times the length of the first type of burst.

Abstract: A host device is coupled to a peripheral device such as a multi media card or the like, where the peripheral device includes a solid state data storage segment. The peripheral device has means for initiating a defragmentation function, such as registers for comparing a current performance measure against a threshold performance metric, or block validity parameters received form the host device for the data storage segment of the peripheral device. Once met, the means for initiating cause a defragmentation function to execute on the data storage segment. A logical layer of the data storage segment is accessed by the host device and a physical layer of the data storage segment is accessed by the peripheral device. The defragmentation program may be resident on either the host or peripheral device. Defragmentation may be enabled to execute automatically once initiated, such as by a continuous or periodic background scan of current performance of the data storage segment.

Abstract: An integrated circuit, such as a dynamic RAM, includes a plurality of terminals for coupling to signal lines. One of the signal lines is an input signal line that conveys a clock signal, and at least one other signal line is also an input signal line that conveys information that is encoded by a level of the at least one other signal line at n consecutive edge transitions of the clock signal, where n?2.

Abstract: A method for checking usable width of a data bus linking a host device and a memory card. Preferably, at the boot up process the host device sends a test bit pattern to the memory card through the data bus. The test bit pattern can be (1010 . . . ) or (0101 . . . ). Upon receiving the test bit pattern, the memory card sends a response bit pattern to the host device through the same data bus. The response bit pattern is complement to the test bit pattern so as to allow the host device to compare the response bit pattern with the test bit pattern, and determines the usable width of the data bus based on the comparison result.

Abstract: A method, apparatus, system, and software product are presented for stopping a continuous burst, or a maximum supported burst, that is used to read from or write to a memory. An indication is provided to release a data bus. Subsequently, the data bus is released in response to the indication, but only after a lapse of time that substantially eliminates unneeded data cycles.

Abstract: A circuit has a first memory, which may be a flash memory or a mass memory, and a random access memory RAM that is distinct from the first memory. A central processing unit CPU couples the first memory to the RAM. Means for encrypting and decrypting in the circuit couples the first memory to the RAM, and is for encrypting and decrypting data between the first memory and the RAM autonomously of the CPU. Preferably, a microprocessor is the means for encrypting and decrypting, and operates to also autonomously read and write to and from, as well as erase from, the RAM. The CPU may be coupled to the first memory and the RAM directly or only through the means for encrypting and decrypting. A device, method, and computer program product are also detailed.

Abstract: A method for addressing dynamic random access memory, with providing a row address and a column address to addressing terminals of the memory, in intervals provided by a timing clock signal, to allow increasing address bus bandwidth without increasing the number of address terminals; the inventive method provides—dividing the row address and/or the column address into parts, and providing the respective parts to the address terminals at a rising, and a falling edge of the timing clock signal.

Abstract: Accessing data stored in a memory device through an interface, with addressing data on the memory device through at least one address bus, controlling at least data flow to and from the memory device through at least one command bus, and transferring data to and from the memory through at least one data bus wherein commands on the command bus are adjusted depending on the type of memory connected to the interface.

Abstract: A method for checking usable width of a data bus linking a host device and a memory card. Preferably, at the boot up process the host device sends a test bit pattern to the memory card through the data bus. The test bit pattern can be (1010 . . . ) or (0101 . . . ). Upon receiving the test bit pattern, the memory card sends a response bit pattern to the host device through the same data bus. The response bit pattern is complement to the test bit pattern so as to allow the host device to compare the response bit pattern with the test bit pattern, and determines the usable width of the data bus based on the comparison result.

Abstract: The invention relates in general to a method for accessing data stored in a dynamic random access memory. To enable flexible use of different types of memory modules, the invention provides addressing data through at least one address bus, controlling at least data flow to and from the dynamic random access memory through at least one control bus, transferring data to and from the dynamic random access memory through at least one data bus, and clocking the dynamic random access memory through at least one clock input, wherein transferring data to and from the dynamic random access memory through the data bus is operated at a variable data flow rate such that the number of data bits transferred on the data bus within one clock cycle is adjustable through at least one command on the control bus.

Abstract: An integrated circuit, such as a dynamic RAM, includes a plurality of terminals for coupling to signal lines. One of the signal lines is an input signal line that conveys a clock signal, and at least one other signal line is also an input signal line that conveys information that is encoded by a level of the at least one other signal line at n consecutive edge transitions of the clock signal, where n?2.

Abstract: A method for checking usable width of a data bus linking a host device and a memory card. Preferably, at the boot up process the host device sends a test bit pattern to the memory card through the data bus. The test bit pattern can be (1010 . . . ) or (0101 . . . ). Upon receiving the test bit pattern, the memory card sends a response bit pattern to the host device through the same data bus. The response bit pattern is complement to the test bit pattern so as to allow the host device to compare the response bit pattern with the test bit pattern, and determines the usable width of the data bus based on the comparison result.

Abstract: A hardware unit (2) for operating memory components comprises a memory controller, a bus and a plurality of interface pins 3–6. The bus is connected to the memory controller and to the interface pins. In order to enable a flexible employment of the hardware unit, the memory controller determines the number of memory components (21,31,41,42,51,52,61,62) connected to the interface pins. In case at least one memory component is determined, the memory controller divides the capacity of the bus into as many portions as there are connected memory components, allocates each portion to another group of interface pins to which a separate memory component is connected, and exchanges signals via the bus and the interface pins separately with each connected memory component. The invention relates equally to an electronic device 1 comprising such a hardware unit and to a corresponding method.