Abstract: A method for addressing dynamic random access memory, with providing a row address and a column address to addressing terminals of the memory, in intervals provided by a timing clock signal, to allow increasing address bus bandwidth without increasing the number of address terminals; the inventive method provides—dividing the row address and/or the column address into parts, and providing the respective parts to the address terminals at a rising, and a falling edge of the timing clock signal.

Abstract: The invention relates to a memory unit with at least two memory areas for storing data, first terminals for accessing data within the memory areas, and second terminals for accessing data within the memory areas. To provide multi-purpose access to the memory, the memory unit provides at least two access control means for providing selectively sole addressing and accessing data through one of the terminals, or individual addressing and accessing data through each of the terminals, respectively.

Abstract: The present invention describes a novel methodology for a direct communication between a memory module and a processor of an electronic device (e.g., a mobile phone) using a fast non-volatile random access memory (NVRAM) provided in that memory module. New NVRAM technologies make it possible to have a single memory unit supporting a baseband operation of the electronic device such as the mobile phone. This is possible because NVRAMs are non-volatile (no need for a separate NOR) and fast (equivalent to a DRAM speed). This invention defines ways to connect the fast NVRAM to a baseband communication line through an existing mobile double data rate (DDR) interface. The invention also demonstrates flexibility and extended capabilities of the NVRAM approach by using the NVRAMs in combination with additional optional components such as a mass memory, a dynamic random access memory (DRAM) and an application-specific integration circuit.

Abstract: A method for refreshing memory cells in a dynamic memory includes dividing the information stored therein at a given time into information to be maintained and information not requiring maintenance, wherein at least some of such memory cells containing information not requiring maintenance are left unrefreshed. In the method application programs are executed. The memory cells of the dynamic memory are divided into two or more blocks which can be refreshed irrespective of each other. Information on the location of each application program to be executed is stored, as well as on the quantity of memory allocated by each application program to be executed. In the method it is further determined on the basis of said stored information which of said memory blocks contains information requiring maintenance, wherein other memory blocks remains unrefreshed. The invention also relates to an electronic device.

Abstract: A method for checking usable width of a data bus linking a host device and a memory card. Preferably, at the boot up process the host device sends a test bit pattern to the memory card through the data bus. The test bit pattern can be (1010 . . . ) or (0101 . . . ). Upon receiving the test bit pattern, the memory card sends a response bit pattern to the host device through the same data bus. The response bit pattern is complement to the test bit pattern so as to allow the host device to compare the response bit pattern with the test bit pattern, and determines the usable width of the data bus based on the comparison result.

Abstract: The present invention relates to a method for connecting a memory component to an electronic device by a connection bus. At least a first interface protocol and a second interface protocol are available on the connection bus, wherein the memory component is recognized. On the basis of the recognition, it is determined, if the first interface protocol or said second interface protocol are available in the memory component, wherein on the basis of the recognition, one of the protocols available in the memory component is selected for use on the connection bus. The invention also relates to a system, in which the method is applied, as well as an electronic device, and a bus connection.

Abstract: A hardware unit (2) for operating memory components comprises a memory controller, a bus and a plurality of interface pins 3-6. The bus is connected to the memory controller and to the interface pins. In order to enable a flexible employment of the hardware unit, the memory controller determines the number of memory components (21,31,41,42,51,52,61,62) connected to the interface pins. In case at least one memory component is determined, the memory controller divides the capacity of the bus into as many portions as there are connected memory components, allocates each portion to another group of interface pins to which a separate memory component is connected, and exchanges signals via the bus and the interface pins separately with each connected memory component. The invention relates equally to an electronic device 1 comprising such a hardware unit and to a corresponding method.

Abstract: The present invention relates to a method for detecting the bus width of a peripheral device (12) connected to an electronic device (1). At least one bus width from a defined set of bus widths is available in the peripheral device (12). In the method, for detecting the bus widths available for the peripheral device (12), one or more indicators (17, DAT3) formed in the peripheral device (12) are used, which indirectly indicate which one or ones of said set of bus widths are available in the peripheral device (12). The invention also relates to a system, in which the method is applied, as well as an electronic device (1) and a peripheral device (12).

Abstract: The invention relates to a method for downloading control software/operating systems of user interfaces into an electronic device (1), which comprises two or more processor blocks (2a, 2b), where in at least two processor blocks (2a, 2b) a user interface (UI1, UI2) is used. Furthermore, one or more operating systems are executed in the electronic device (1). The downloading is executed via one said processor block (2a, 2b), wherein the control software/operating systems are downloaded into said one processor block (2a, 2b), from which the control software/operating systems related to other user interfaces are loaded into said other processor blocks (2a, 2b).

Abstract: A memory controller for controlling the transfer of data to and from a memory array, wherein the memory array includes a first type of memory and a second type of memory, the first type having a different signalling protocol from the second type of memory, wherein the memory controller comprises: an address decoder having an input for receiving a memory access request, said memory access request including the address of the memory array to be accessed, and an output for outputting the address of the memory array to be accessed; a first sub-controller for generating a plurality of memory interface signals for controlling the first type of memory, said first sub-controller being operated in response to addresses within a first range of addresses output by the address decoder; and a second sub-controller for generating a plurality of memory interface signals for controlling the second type of memory, said second sub-controller being operated in response to addresses within a second, non-overlapping range of a

Abstract: The invention relates to a method for downloading control software/operating systems of user interfaces into an electronic device (1), which comprises two or more processor blocks (2a, 2b), where in at least two processor blocks (2a, 2b) a user interface (UI1, UI2) is used. Furthermore, one or more operating systems are executed in the electronic device (1). The downloading is executed via one said processor block (2a, 2b), wherein the control software/operating systems are downloaded into said one processor block (2a, 2b), from which the control software/operating systems related to other user interfaces are loaded into said other processor blocks (2a, 2b).

Abstract: A memory controller for controlling the transfer of data to and from a memory array, wherein the memory array includes a first type of memory and a second type of memory, the first type having a different signalling protocol from the second type of memory, wherein the memory controller comprises: