Abstract: Embodiments described herein relate to methods for forming an air gap interconnect. A metal spacer layer is conformally deposited on a substrate having mandrel structures formed thereon. The metal spacer layer is etched to form spacer features and the mandrel structures are removed from the substrate. Various other dielectric deposition, patterning and etching steps may be performed to desirably pattern materials present on the substrate. Ultimately, a trench is formed between adjacent spacer features and a capping layer is deposited over the trench to form an air gap between the adjacent spacer features. For packaging purposes, an interconnect via may be configured to contact at least one of the spacer features adjacent the air gap.

Abstract: Methods and apparatus for forming a metal silicide as nanowires for back-end interconnection structures for semiconductor applications are provided. In one embodiment, the method includes forming a metal silicide stack comprising as plurality of metal silicide layers on a substrate by a chemical vapor deposition process or a physical vapor deposition process, thermal treating the metal silicide stack in a processing chamber, applying a microwave power in the processing chamber while thermal treating the metal silicide layer; and maintaining a substrate temperature less than 400 degrees Celsius while thermal treating the metal silicide layer.

Abstract: Methods for direct deposition of a metal silicide nanowire for back-end interconnection structures for semiconductor applications are provided. In one embodiment, the method includes positioning a substrate in a processing region of a process chamber, the substrate having a first surface comprising a non-dielectric material; and a dielectric layer formed on the first surface. An opening is formed in the dielectric layer, the opening exposing at least a portion of the first surface, the opening having sidewalls. A metal silicide seed is deposited in the opening using a PVD process, wherein the PVD process is performed with either no bias or a bias which creates deposition on the sidewall which is less than 1% of the deposition on the first surface. A metal silicide layer is then selectively deposited on the metal silicide seed using a metal-silicon organic precursor, creating the metal silicide nanowire.

Abstract: A method is provided for forming an interconnect structure for use in semiconductor devices. The method starts with forming a low-k bulk dielectric layer on a substrate and then forming a trench in the low-k bulk dielectric layer. A liner layer is formed on the low-k bulk dielectric layer being deposited conformally to the trench. A copper layer is formed on the liner layer filling the trench. Portions of the copper layer and liner layer are removed to form an upper surface of the low-k bulk dielectric layer, the liner layer, and the copper layer. A metal containing dielectric layer is formed on the upper surface of the low-k bulk dielectric layer, the liner layer, and the copper layer.

Abstract: Embodiments of the disclosure generally provide a method of forming a reduced dimension pattern in a hardmask that is optically matched to an overlying photoresist layer. The method generally comprises of application of a dimension shrinking conformal carbon layer over the field region, sidewalls, and bottom portion of the patterned photoresist and the underlying hardmask at temperatures below the decomposition temperature of the photoresist. The methods and embodiments herein further involve removal of the conformal carbon layer from the bottom portion of the patterned photoresist and the hardmask by an etch process to expose the hardmask, etching the exposed hardmask substrate at the bottom portion, followed by the simultaneous removal of the conformal carbon layer, the photoresist, and other carbonaceous components. A hardmask with reduced dimension features for further pattern transfer is thus yielded.

Abstract: Embodiments of the present invention generally relate to methods for forming a metal structure and passivation layers. In one embodiment, metal columns are formed on a substrate. The metal columns are doped with manganese, aluminum, zirconium, or hafnium. A dielectric material is deposited over and between the metal columns and then cured to form a passivation layer on vertical surfaces of the metal columns.

Abstract: A method for forming an air gap structure in an integrated layer stack includes dry etching a mold layer disposed on the stack in a processing system under vacuum. The mold layer is disposed between one or more interconnects, and the process of dry etching of the mold layer exposes at least a portion of the interconnects. The method also includes depositing a liner layer over the exposed portion of the interconnects. In another embodiment, a method for forming an air gap structure in an integrated layer stack includes dry etching an oxide mold layer disposed on the stack in an a first processing chamber in a processing system under vacuum. The method also includes depositing a low-k material liner layer over the interconnects, wherein the liner has a thickness of less than about 2 nanometers. The methods disclosed herein are performed in a processing system without breaking vacuum.

Abstract: Embodiments described herein relate to methods for forming an air gap interconnect. A metal spacer layer is conformally deposited on a substrate having mandrel structures formed thereon. The metal spacer layer is etched to form spacer features and the mandrel structures are removed from the substrate. Various other dielectric deposition, patterning and etching steps may be performed to desirably pattern materials present on the substrate. Ultimately, a trench is formed between adjacent spacer features and a capping layer is deposited over the trench to form an air gap between the adjacent spacer features. For packaging purposes, an interconnect via may be configured to contact at least one of the spacer features adjacent the air gap.

Abstract: Methods for eliminating early exposure of a conductive layer in a dual damascene structure and for etching a dielectric barrier layer in the dual damascene structure are provided. In one embodiment, a method for etching a dielectric barrier layer disposed on a substrate includes patterning a substrate having a dielectric bulk insulating layer disposed on a dielectric barrier layer using a hardmask layer disposed on the dielectric bulk insulating layer as an etching mask, exposing a portion of the dielectric barrier layer after removing the dielectric bulk insulating layer uncovered by the dielectric bulk insulating layer, removing the hardmask layer from the substrate, and subsequently etching the dielectric barrier layer exposed by the dielectric bulk insulating layer.

Abstract: Methods for forming a passivation protection structure on a metal line layer formed in an insulating material in an interconnection structure are provided. In one embodiment, a method for forming passivation protection on a metal line in an interconnection structure for semiconductor devices includes selectively forming a metal capping layer on a metal line bounded by a dielectric bulk insulating layer in an interconnection structure formed on a substrate in a processing chamber incorporated in a multi-chamber processing system, in-situ forming a barrier layer on the substrate in the processing chamber; wherein the barrier layer is a metal dielectric layer, and forming a dielectric capping layer on the barrier layer in the multi-chamber processing system.

Abstract: Methods and apparatuses for forming a dual damascene structure utilizing a selective protection process to protect vias and/or trenches in the dual damascene structure while removing a hardmask layer from the dual damascene structure. In one embodiment, a method for removing a patterned hardmask layer from a substrate includes forming an organic polymer material on a dual damascene structure that exposes substantially a patterned hardmask layer disposed on an upper surface of the dual damascene structure, removing the patterned hardmask layer on the substrate, and removing the organic polymer material from the substrate.

Abstract: Embodiments of the disclosure generally provide a method of forming a reduced dimension pattern in a hardmask that is optically matched to an overlying photoresist layer. The method generally comprises of application of a dimension shrinking conformal carbon layer over the field region, sidewalls, and bottom portion of the patterned photoresist and the underlying hardmask at temperatures below the decomposition temperature of the photoresist. The methods and embodiments herein further involve removal of the conformal carbon layer from the bottom portion of the patterned photoresist and the hardmask by an etch process to expose the hardmask, etching the exposed hardmask substrate at the bottom portion, followed by the simultaneous removal of the conformal carbon layer, the photoresist, and other carbonaceous components. A hardmask with reduced dimension features for further pattern transfer is thus yielded.

Abstract: Embodiments of the present invention generally relate to methods for forming a metal structure and passivation layers. In one embodiment, metal columns are formed on a substrate. The metal columns are doped with manganese, aluminum, zirconium, or hafnium. A dielectric material is deposited over and between the metal columns and then cured to form a passivation layer on vertical surfaces of the metal columns.

Abstract: Embodiments described herein provide a method for sealing a porous low-k dielectric film. The method includes forming a sealing layer on the porous low-k dielectric film using a cyclic process. The cyclic process includes repeating a sequence of depositing a sealing layer on the porous low-k dielectric film and treating the sealing layer until the sealing layer achieves a predetermined thickness. The treating of each intermediate sealing layer generates more reactive sites on the surface of each intermediate sealing layer, which improves the quality of the resulting sealing layer.

Abstract: Methods and apparatuses for forming a dual damascene structure utilizing a selective protection process to protect vias and/or trenches in the dual damascene structure while removing a hardmask layer from the dual damascene structure. In one embodiment, a method for removing a patterned hardmask layer from a substrate includes forming an organic polymer material on a dual damascene structure that exposes substantially a patterned hardmask layer disposed on an upper surface of the dual damascene structure, removing the patterned hardmask layer on the substrate, and removing the organic polymer material from the substrate.

Abstract: Embodiments of the present invention generally relate to methods for forming a metal structure and passivation layers. In one embodiment, metal columns are formed on a substrate. The metal columns are doped with manganese, aluminum, zirconium, or hafnium. A dielectric material is deposited over and between the metal columns and then cured to form a passivation layer on vertical surfaces of the metal columns.

Abstract: Embodiments described herein relate to methods for forming an air gap interconnect. A metal spacer layer is conformally deposited on a substrate having mandrel structures formed thereon. The metal spacer layer is etched to form spacer features and the mandrel structures are removed from the substrate. Various other dielectric deposition, patterning and etching steps may be performed to desirably pattern materials present on the substrate. Ultimately, a trench is formed between adjacent spacer features and a capping layer is deposited over the trench to form an air gap between the adjacent spacer features. For packaging purposes, an interconnect via may be configured to contact at least one of the spacer features adjacent the air gap.

Abstract: Embodiments of the present invention provide methods for forming an interconnection structure in semiconductor devices without breaking vacuum with minimum oxidation/atmosphere exposure. In one embodiment, a method for forming an interconnection structure for semiconductor devices includes supplying a barrier layer etching gas mixture into a first processing chamber having a substrate disposed therein to etch portions of a barrier layer exposed by a patterned metal layer until the underlying substrate is exposed, the first processing chamber disposed in a processing system, and forming a liner layer on the substrate covering the etched barrier layer in a second processing chamber disposed in the processing system.

Abstract: Methods for forming a passivation protection structure on a metal line layer formed in an insulating material in an interconnection structure are provided. In one embodiment, a method for forming passivation protection on a metal line in an interconnection structure for semiconductor devices includes selectively forming a metal capping layer on a metal line bounded by a dielectric bulk insulating layer in an interconnection structure formed on a substrate in a processing chamber incorporated in a multi-chamber processing system, in-situ forming a barrier layer on the substrate in the processing chamber; wherein the barrier layer is a metal dielectric layer, and forming a dielectric capping layer on the barrier layer in the multi-chamber processing system.

Abstract: An interconnect structure for use in semiconductor devices and a method for fabricating the same is described. The method includes positioning a substrate in a vacuum processing chamber. The substrate has an exposed copper surface and an exposed low-k dielectric surface. A metal layer is formed over the copper surface but not over the low-k dielectric surface. A metal-based dielectric layer is formed over the metal layer and the low-k dielectric layer.