Patents by Inventor Mei-Ling Chen
Mei-Ling Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140131793Abstract: A method for manufacturing a rectifier with a vertical MOS structure is provided. A first trench structure and a first mask layer are formed at a first side of the semiconductor substrate. A second trench structure is formed in the second side of the semiconductor substrate. A gate oxide layer, a polysilicon structure and a metal sputtering layer are sequentially formed on the second trench structure. The rectifier further includes a wet oxide layer and a plurality of doped regions. The wet oxide layer is formed on a surface of the first multi-trench structure and in the semiconductor substrate. The doping regions are formed on a region between the semiconductor substrate and the second trench structure, and located beside the mask layer. The metal sputtering layer is formed on the first mask layer corresponding to the first trench structure.Type: ApplicationFiled: January 8, 2014Publication date: May 15, 2014Applicant: PFC DEVICE CORP.Inventors: Kuo-Liang Chao, Mei-Ling Chen, Hung-Hsin Kuo
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Patent number: 8704298Abstract: A MOS diode includes a substrate with a mesa, a P-type semiconductor region with etched shallow trench surrounding the mesa, that cause an increasing metal contact area to reduce Vf value, a gate oxide layer arranged on the mesa, a polysilicon layer arranged on the gate oxide layer, and a shielding oxide layer arranged on the polysilicon layer. The termination structure includes a trench, an oxide layer arranged at least within the trench, at least one sidewall polysilicon layer arranged on the oxide layer within the trench. In the MOS diode, the shielding oxide layer is thicker than the gate oxide layer to prevent leaking current. The oxide layer and the sidewall polysilicon layer can enhance the reverse voltage tolerance of the MOS diode. A metal layer covers the polysilicon region, shielding oxide layer, semiconductor regions with etched shallow trench, termination region and some parts outside the termination region.Type: GrantFiled: March 14, 2013Date of Patent: April 22, 2014Assignee: PFC Device Corp.Inventors: Kuo-Liang Chao, Mei-Ling Chen, Lung-Ching Kao, Hung-Hsin Kuo
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Patent number: 8680590Abstract: A multi-trench termination structure for semiconductor device is disclosed, where the semiconductor device includes a semiconductor substrate and an active structure region. The multi-trench termination structure includes multiple trenches defined on an exposed face of the semiconductor substrate, a first mask layer formed on a partial exposed surface of the semiconductor substrate and corresponding to a termination structure region of the semiconductor device, a gate insulation layer formed in the trenches, a conductive layer formed on the gate insulation layer and protruding out of the exposed surface of the semiconductor substrate, and a metal layer formed over the first mask layer and conductive layer on the termination structure region of the semiconductor device.Type: GrantFiled: March 2, 2012Date of Patent: March 25, 2014Assignee: PFC Device Corp.Inventors: Lung-Ching Kao, Mei-Ling Chen, Kuo-Liang Chao, Hung-Hsin Kuo
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Publication number: 20140077328Abstract: A trench Schottky rectifier device includes a substrate having a first conductivity type, a plurality of trenches formed in the substrate, and an insulating layer formed on sidewalls of the trenches. The trenches are filled with conductive structure. There is an electrode overlying the conductive structure and the substrate, and thus a Schottky contact forms between the electrode and the substrate. A plurality of embedded doped regions having a second conductivity type are formed in the substrate and located under the trenches. Each doped region and the substrate form a PN junction to pinch off current flowing toward the Schottky contact so as to suppress current leakage.Type: ApplicationFiled: November 15, 2013Publication date: March 20, 2014Applicant: PFC DEVICE CORP.Inventors: Kou-Liang CHAO, Mei-Ling CHEN, Tse-Chuan SU, Hung-Hsin KUO
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Patent number: 8664701Abstract: A method for manufacturing a rectifier with a vertical MOS structure is provided. A first trench structure and a first mask layer are formed at a first side of the semiconductor substrate. A second trench structure is formed in the second side of the semiconductor substrate. A gate oxide layer, a polysilicon structure and a metal sputtering layer are sequentially formed on the second trench structure. The rectifier further includes a wet oxide layer and a plurality of doped regions. The wet oxide layer is formed on a surface of the first multi-trench structure and in the semiconductor substrate. The doping regions are formed on a region between the semiconductor substrate and the second trench structure, and located beside the mask layer. The metal sputtering layer is formed on the first mask layer corresponding to the first trench structure.Type: GrantFiled: April 13, 2012Date of Patent: March 4, 2014Assignee: PFC Device Corp.Inventors: Kuo-Liang Chao, Mei-Ling Chen, Hung-Hsin Kuo
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Publication number: 20140030882Abstract: A multi-trench termination structure for semiconductor device is disclosed, where the semiconductor device includes a semiconductor substrate and an active structure region. The multi-trench termination structure includes multiple trenches defined on an exposed face of the semiconductor substrate, a first mask layer formed on a partial exposed surface of the semiconductor substrate and corresponding to a termination structure region of the semiconductor device, a gate insulation layer formed in the trenches, a conductive layer formed on the gate insulation layer and protruding out of the exposed surface of the semiconductor substrate, and a metal layer formed over the first mask layer and conductive layer on the termination structure region of the semiconductor device.Type: ApplicationFiled: September 26, 2013Publication date: January 30, 2014Applicant: PFC DEVICE CORP.Inventors: Lung-Ching KAO, Mei-Ling CHEN, Kuo-Liang CHAO, Hung-Hsin KUO
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Publication number: 20140004681Abstract: A trench isolation metal-oxide-semiconductor (MOS) P-N junction diode device and a manufacturing method thereof are provided. The trench isolation MOS P-N junction diode device is a combination of an N-channel MOS structure and a lateral P-N junction diode, wherein a polysilicon-filled trench oxide layer is buried in the P-type structure to replace the majority of the P-type structure. As a consequence, the trench isolation MOS P-N junction diode device of the present invention has the benefits of the Schottky diode and the P-N junction diode. That is, the trench isolation MOS P-N junction diode device has rapid switching speed, low forward voltage drop, low reverse leakage current and short reverse recovery time.Type: ApplicationFiled: September 5, 2013Publication date: January 2, 2014Applicant: PFC DEVICE CORP.Inventors: Mei-Ling Chen, Hung-Hsin Kuo, Kuo-Liang Chao
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Patent number: 8618626Abstract: A trench Schottky rectifier device includes a substrate having a first conductivity type, a plurality of trenches formed in the substrate, and an insulating layer formed on sidewalls of the trenches. The trenches are filled with conductive structure. There is an electrode overlying the conductive structure and the substrate, and thus a Schottky contact forms between the electrode and the substrate. A plurality of embedded doped regions having a second conductivity type are formed in the substrate and located under the trenches. Each doped region and the substrate form a PN junction to pinch off current flowing toward the Schottky contact so as to suppress current leakage.Type: GrantFiled: October 12, 2010Date of Patent: December 31, 2013Assignee: PFC Device CorporationInventors: Kou-Liang Chao, Mei-Ling Chen, Tse-Chuan Su, Hung-Hsin Kuo
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Publication number: 20130277853Abstract: Semiconductor devices, methods of manufacture thereof, and methods of forming conductive features thereof are disclosed. A semiconductor device includes an insulating material layer disposed over a workpiece. The insulating material layer includes a silicon-containing material comprising about 13% or greater of carbon (C). A conductive feature is disposed within the insulating material layer. The conductive feature includes a capping layer disposed on a top surface thereof.Type: ApplicationFiled: April 20, 2012Publication date: October 24, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hui-Chun Yang, Mei-Ling Chen, Keng-Chu Lin, Joung-Wei Liou
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Publication number: 20130273732Abstract: An Active Energy Assist (AEA) baking chamber includes an AEA light source assembly and a heater pedestal. The AEA baking chamber further includes a controller for controlling a power input to the AEA light source assembly and a power input to the heater pedestal. A method of forming interconnects on a substrate includes etching a substrate and wet cleaning the etched substrate. The method further includes active energy assist (AEA) baking the substrate after the wet-cleaning. The AEA baking includes placing the substrate on a heater pedestal in an AEA chamber, exposing the substrate to light having a wavelength equal to or greater than 400 nm, wherein said light is emitted by a light source and controlling the light source and the heater pedestal using a controller.Type: ApplicationFiled: June 11, 2013Publication date: October 17, 2013Inventors: Chung-Chi KO, Chia Cheng CHOU, Keng-Chu LIN, Joung-Wei LIOU, Shwang-Ming JENG, Mei-Ling CHEN
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Patent number: 8558315Abstract: A trench isolation metal-oxide-semiconductor (MOS) P-N junction diode device and a manufacturing method thereof are provided. The trench isolation MOS P-N junction diode device is a combination of an N-channel MOS structure and a lateral P-N junction diode, wherein a polysilicon-filled trench oxide layer is buried in the P-type structure to replace the majority of the P-type structure. As a consequence, the trench isolation MOS P-N junction diode device of the present invention has the benefits of the Schottky diode and the P-N junction diode. That is, the trench isolation MOS P-N junction diode device has rapid switching speed, low forward voltage drop, low reverse leakage current and short reverse recovery time.Type: GrantFiled: July 26, 2011Date of Patent: October 15, 2013Assignee: PFC Device CorporationInventors: Mei-Ling Chen, Hung-Hsin Kuo, Kou-Liang Chao
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Publication number: 20130249043Abstract: A wide trench termination structure for semiconductor device includes a wide trench structure defined on a semiconductor substrate and having a width larger than that of narrow trench structures on an active region of the semiconductor device, an oxide layer arranged on an inner face of the wide trench structure, at least one trench polysilicon layer arranged on the oxide layer and on inner sidewall of the wide trench structure, a metal layer arranged on the oxide layer not covered by the trench polysilicon layer and on the trench polysilicon layer, and a field oxide layer arranged on the semiconductor substrate and outside the wide trench structure.Type: ApplicationFiled: January 9, 2013Publication date: September 26, 2013Applicant: PFC DEVICE CORP.Inventors: Hung-Hsin KUO, Mei-Ling CHEN, Kuo-Liang CHAO
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Patent number: 8536283Abstract: A varnish composition includes (1) a benzoxazine resin having highly symmetric molecular structure; (2) at least one of naphthol novolac resins, aniline novolac resins and phenolic novolac resins; (3) fillers. The benzoxazine resin having highly symmetric molecular structure, and the at least one of naphthol novolac resins, aniline novolac resins and phenolic novolac resins contribute to increase the glass transition temperature of the varnish composition, while decrease the coefficient of thermal expansion and moisture absorbability due to their small and highly symmetric molecular structures. A copper substrate can meet the requirement of high glass transition temperature (TMA?200° C.) and low coefficient of thermal expansion (?1/??30/135 (?m/m° C.). Therefore, the composition of the invention can be widely used as high-performance electronic material.Type: GrantFiled: February 25, 2011Date of Patent: September 17, 2013Assignee: Nan Ya Plastics CorporationInventors: Ming-Jen Tzou, Chi-Cheng Chen, Mei-Ling Chen
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Publication number: 20130228891Abstract: A multi-trench termination structure for semiconductor device is disclosed, where the semiconductor device includes a semiconductor substrate and an active structure region. The multi-trench termination structure includes multiple trenches defined on an exposed face of the semiconductor substrate, a first mask layer formed on a partial exposed surface of the semiconductor substrate and corresponding to a termination structure region of the semiconductor device, a gate insulation layer formed in the trenches, a conductive layer formed on the gate insulation layer and protruding out of the exposed surface of the semiconductor substrate, and a metal layer formed over the first mask layer and conductive layer on the termination structure region of the semiconductor device.Type: ApplicationFiled: March 2, 2012Publication date: September 5, 2013Inventors: Lung-Ching Kao, Mei-Ling Chen, Kuo-Liang Chao, Hung-Hsin Kuo
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Patent number: 8481412Abstract: A method of and apparatus for forming interconnects on a substrate includes etching patterns in ultra-low k dielectric and removing moisture from the ultra-low k dielectric using active energy assist baking. During active energy assist baking, the ultra-low k dielectric is heated and exposed to light having only wavelengths greater than 400 nm for about 1 to about 20 minutes at a temperature of about 300 to about 400 degrees Celsius. The active energy assist baking is performed after wet-cleaning or after chemical mechanical polishing, or both.Type: GrantFiled: September 29, 2010Date of Patent: July 9, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Chi Ko, Chia Cheng Chou, Keng-Chu Lin, Joung-Wei Liou, Shwang-Ming Jeng, Mei-Ling Chen
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Patent number: 8405184Abstract: A trench Schottky diode and its manufacturing method are provided. The trench Schottky diode includes a semiconductor substrate having therein a plurality of trenches, a gate oxide layer, a polysilicon structure, a guard ring and an electrode. At first, the trenches are formed in the semiconductor substrate by an etching step. Then, the gate oxide layer and the polysilicon structure are formed in the trenches and protrude above a surface of the semiconductor substrate. The guard ring is formed to cover a portion of the resultant structure. At last, the electrode is formed above the guard ring and the other portion not covered by the guard ring. The protruding gate oxide layer and the protruding polysilicon structure can avoid cracks occurring in the trench structure.Type: GrantFiled: June 28, 2010Date of Patent: March 26, 2013Assignee: PFC Device CorporationInventors: Kou-Liang Chao, Hung-Hsin Kuo, Tse-Chuan Su, Mei-Ling Chen
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Patent number: 8386161Abstract: Route planning methods and systems are provided. First, an input corresponding to a specific region is received via an input unit of a personal navigation device. Then, a first predefined location located in the specific region is determined. A first route from a first current position of the device to the first predefined location is planned.Type: GrantFiled: September 5, 2009Date of Patent: February 26, 2013Assignee: MiTAC International Corp.Inventor: Mei-Ling Chen
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Patent number: 8378365Abstract: A light emitting diode (LED) package including a carrier, at least one LED chip, and a light guide element is provided. The LED chip is disposed on the carrier. The light guide element including a light transmissive body, a light integration part, a reflective film, and a support part is disposed on the carrier and above the LED chip. The light integration part connected to the light transmissive body and disposed between the light transmissive body and the LED chip has a light incident surface facing the LED chip and at least one side. The side connects the light transmissive body and the light incident surface. The reflective film is disposed on the side. The support part leaning on the carrier is connected to the light transmissive body and surrounds the light integration part. The light transmissive body, the light integration part, and the support part are integrally formed.Type: GrantFiled: September 15, 2009Date of Patent: February 19, 2013Assignee: Young Optics Inc.Inventors: Mei-Ling Chen, Wen-Chieh Wen, Haw-Woei Pan, Chao-Shun Chen
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Patent number: 8350246Abstract: A structure of a porous low-k layer is described, comprising a bottom portion and a body portion of the same atomic composition, wherein the body portion is located on the bottom portion, and the bottom portion has a density higher than the density of the body portion. An interconnect structure is also described, including the above porous low-k layer, and a conductive layer filling up a damascene opening in the porous low-k layer.Type: GrantFiled: March 2, 2011Date of Patent: January 8, 2013Assignee: United Microelectronics Corp.Inventors: Mei-Ling Chen, Kuo-Chih Lai, Su-Jen Sung, Chien-Chung Huang, Yu-Tsung Lai
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Publication number: 20120261751Abstract: A method for manufacturing a rectifier with a vertical MOS structure is provided. A first trench structure and a first mask layer are formed at a first side of the semiconductor substrate. A second trench structure is formed in the second side of the semiconductor substrate. A gate oxide layer, a polysilicon structure and a metal sputtering layer are sequentially formed on the second trench structure. The rectifier further includes a wet oxide layer and a plurality of doped regions. The wet oxide layer is formed on a surface of the first multi-trench structure and in the semiconductor substrate. The doping regions are formed on a region between the semiconductor substrate and the second trench structure, and located beside the mask layer. The metal sputtering layer is formed on the first mask layer corresponding to the first trench structure.Type: ApplicationFiled: April 13, 2012Publication date: October 18, 2012Applicant: PFC DEVICE CORP.Inventors: Kou-Liang Chao, Mei-Ling Chen, Hung-Hsin Kuo