Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Abstract: High-speed data transfer rates are provided between a central office and customer premise equipment with a multiplexer that is interposed between the central office and the customer premise equipment, and that functions as a remote access node. The multiplexer communicates at high data rates via downstream data links such as twisted-pair conductors between the multiplexer and the customer premise equipment. By positioning the multiplexer physically close to the customer premise equipment, DSL data rates can be achieved. In one application, the multiplexer assigns a variable number of the upstream data links between the central office and the multiplexer on a dynamic, adaptive, and automatic basis to individual ones of the downstream data links. In this way, unused data link capacity of the upstream data links is used to provide high data transmission rates when required between the multiplexer and the central office.

Abstract: A universal broadband server connected between a plurality of subscriber lines, at least one upstream link, and a central office provides broadband service to a plurality of customer premise equipment devices connected to the plurality of subscriber lines. The universal broadband server may also provides analog modem service to the plurality of customer premise equipment devices connected to the plurality of subscriber lines. A dynamic bandwidth allocation method adjusts the transmit power and bandwidth at which the universal broadband server communicates with the plurality of customer premise equipment devices in consideration of the maximum available bandwidth provided by the at least one upstream link, and the maximum available power.

Abstract: A faster modem apparatus communicates with customer premise equipment according to a variety of communication protocols. The faster modem apparatus communicates with customer premise equipment comprising an analog soft-modem comprising a codec. A method utilizes an unused portion of the codec operating range to code and decode data signals having frequencies above 4 kHz. The faster modem apparatus also codes and decodes data signals above 4 kHz. The analog soft-modem and the faster modem apparatus transmit and receive coded analog signals at a signal level of greater than ?9 dBm. In one embodiment, the faster modem apparatus is also operative to communicate with additional modems such as dial-up modems and DSL modems. In one embodiment, the faster modem apparatus supports simultaneous voice and data communications.

Abstract: A controller device and method for operating same is disclosed. In one particular exemplary embodiment, the controller device may comprise output driver circuitry and input receiver circuitry. The output driver circuitry may output a value, a first operation code, a block size value, and second operation code. The first operation code may represent an instruction to a memory device to store the value in a register in the memory device. The block size value may indicate an amount of read data to be output by the memory device in response to the second operation code. The second operation code may represent an instruction to the memory device to perform a read operation. The input receiver circuitry may sample a first portion of the read data output by the memory device after a read delay following the outputting of the second operation code.

Abstract: A memory module including an integrated circuit is disclosed. In one particular exemplary embodiment, the memory module may comprise a plurality of memory devices and an integrated circuit device that is coupled to the plurality of memory devices. The integrated circuit device includes a first circuit to receive control information specifying a write operation, and address information specifying a memory location corresponding to the write operation, wherein the memory location is in a first memory device of the plurality of memory devices, and wherein the control information and the address information are received in a multiplexed format. The integrated circuit device also includes a second circuit, including a plurality of output drivers, to output data after a first number of clock cycles of an external clock signal transpire, wherein the data is to be written to the first memory device during the write operation.

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control informastion needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention.

Abstract: An integrated circuit device is disclosed. In one particular exemplary embodiment, the integrated circuit device may comprise a first circuit to receive, in a multiplexed format, control information and address information, wherein the control information specifies a write operation and the address information specifies a location within a memory array for the write operation. The integrated circuit device may also comprise a second circuit that includes a plurality of output drivers to output write data to be written to the memory array during the write operation, wherein the write data is output after a number of clock cycles of an external clock signal transpire, wherein the write data is output in response to the control information, and wherein each output driver of the plurality of output drivers outputs two bits of the write data during a single clock cycle of the external clock signal.

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention.

Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Abstract: In one embodiment, a modular memory device is presented comprising a substrate, a memory array fabricated above the substrate, and first and second circuitry fabricated on the substrate and under the memory array. The first and second circuitry allow the modular memory device to interface with first and second varieties of host devices, respectively. In another embodiment, a modular memory device is presented comprising a substrate, a memory array fabricated above the substrate, memory array support circuitry fabricated on the substrate, and logic circuitry fabricated on the substrate and under the memory array.

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention.

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention.

Abstract: A physical layer router comprises a plurality of subscriber ports, a plurality of dsp pool ports, a switch, isolation circuitry, a tone detector, and control logic. The control logic comprises a microprocessor interface. The physical layer router couples at least some of the plurality of subscriber ports to at least some of the plurality of dsp pool pools. The physical layer router connects every subscriber port not coupled to a dsp pool port to a snoop bus. Tones are detected on the snoop bus. The tones comprise request tones from customer premise equipment devices connected to the plurality of subscriber ports. Exactly one subscriber port is isolated, whereby exactly one customer premise equipment device generating the request tone is isolated. A dsp pool port is coupled to the isolated subscriber port. A fast line acquisition method finds one subscriber port of the plurality of subscriber ports receiving the request tones.

Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Abstract: A synchronous integrated circuit device including a clock receiver to receive an external clock signal and a plurality of output drivers to output data. A first portion of the data is output synchronously with respect to a rising edge transition of the external clock signal. A second portion of the data is output synchronously with respect to a falling edge transition of the external clock signal. In addition, the integrated circuit device includes a delay locked loop, coupled to the plurality of output drivers and the clock receiver, to synchronize the output of the first and second portions of the data with the external clock signal.

Abstract: High-speed data transfer rates are provided between a central office and customer premise equipment with a multiplexer that is interposed between the central office and the customer premise equipment, and that functions as a remote access node. The multiplexer communicates at high data rates via downstream data links such as twisted-pair conductors between the multiplexer and the customer premise equipment. By positioning the multiplexer physically close to the customer premise equipment, DSL data rates can be achieved. In one application, the multiplexer assigns a variable number of the upstream data links between the central office and the multiplexer on a dynamic, adaptive, and automatic basis to individual ones of the downstream data links. In this way, unused data link capacity of the upstream data links is used to provide high data transmission rates when required between the multiplexer and the central office.

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract: A physical layer router comprises a plurality of subscriber ports, a plurality of dsp pool ports, a switch, isolation circuitry, a tone detector, and control logic. The control logic comprises a microprocessor interface. The physical layer router couples at least some of the plurality of subscriber ports to at least some of the plurality of dsp pool pools. The physical layer router connects every subscriber port not coupled to a dsp pool port to a snoop bus. Tones are detected on the snoop bus. The tones comprise request tones from customer premise equipment devices connected to the plurality of subscriber ports. Exactly one subscriber port is isolated, whereby exactly one customer premise equipment device generating the request tone is isolated. A dsp pool port is coupled to the isolated subscriber port. A fast line acquisition method finds one subscriber port of the plurality of subscriber ports receiving the request tones.

Abstract: A universal broadband server connected between a plurality of subscriber lines, at least one upstream link, and a central office provides broadband service to a plurality of customer premise equipment devices connected to the plurality of subscriber lines. The universal broadband server may also provides analog modem service to the plurality of customer premise equipment devices connected to the plurality of subscriber lines. A dynamic bandwidth allocation method adjusts the transmit power and bandwidth at which the universal broadband server communicates with the plurality of customer premise equipment devices in consideration of the maximum available bandwidth provided by the at least one upstream link, and the maximum available power.