Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.

Abstract: A synchronous memory device and methods of operation and controlling such a device. The method of controlling the memory device includes providing block size information to the memory device, synchronously with respect to an external clock signal, wherein the block size information defines an amount of data to be output by the memory device in response to a read request. The method further includes issuing a first read request to the memory device, wherein the memory device receives the first read request synchronously with respect to a transition of the external clock signal.

Abstract: A memory device having a plurality of memory cells, the memory device comprising clock receiver circuitry to receive an external clock signal, and input receiver circuitry to sample, in response to a write request, a first portion of data after a number of clock cycles of the external clock signal transpire. The first portion of data is sampled synchronously with respect to the external clock signal.

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.

Abstract: A method of operation of a memory controller device, the method of operation comprises issuing a write request to a memory device synchronously with respect to an external clock signal, wherein in response to the write request, a memory device inputs first and second portions of data. The method of operation further includes outputting the first portion of data synchronously with respect to a first edge transition of an external clock signal; and outputting the second portion of data from the bus synchronously with respect to a second edge transition of the external clock signal. The first and second edge transitions of the external clock signal are of transitions of the same clock cycle.

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.

Abstract: A method of operation of a memory device. The memory device including a section of memory having a plurality of memory cells. The method of operation comprises receiving a request for a write operation and sampling a first portion of data after a delay time transpires in response to the request for a write operation. A method of controlling the memory device comprises issuing a request for a write operation to the memory device. The memory device samples data after a number of clock cycles of the external clock signal transpire in response to the request. The method of controlling also comprises issuing a first portion of data to the memory device after the number of clock cycles of the external clock signal transpire.

Abstract: A method of controlling a synchronous memory device comprising issuing a write request to the memory device, wherein in response to the write request, the memory device samples first and second portions of data. The first portion of data is provided to the memory device synchronously with respect to a rising edge transition of an external clock signal. A second portion of data is provided to the memory device synchronously with respect to a falling edge transition of the external clock signal. A memory controller for controlling a synchronous memory device comprises output driver circuitry to output data. The output driver circuitry outputs a first portion of data in response to a rising edge transition of the first external clock signal. In addition, the output driver circuitry outputs a second portion of data in response to a falling edge transition of the first external clock signal.

Abstract: A memory system having a master device and a plurality of memory subsystems, including first and second memory subsystems coupled to a first bus. Each memory subsystem includes a plurality of memory devices. The master device transmits a request for a read operation onto the first bus to access data from at least one memory device included in at least one memory subsystem. The first and second memory subsystems each include a transceiver device, a bus, and first and second memory devices. Each transceiver device connects to the first bus. The bus of each memory subsystem connects to each respective transceiver device, wherein each transceiver device is coupled between the first bus and each respective memory subsystem bus. The first and second memory devices in each memory subsystem are coupled respective transceiver devices via respective buses.

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract: A method of controlling a memory device. The method includes providing first block size information to the memory device, wherein the first block size information defines a first amount of data to be input by the memory device in response to a write request. A first portion of the first amount of data is provided to the memory device synchronously with respect to a first transition of an external clock signal. A second portion of the first amount of data is provided to the memory device synchronously with respect to a second transition of the external clock signal. The method further includes issuing a write request to the memory device, wherein in response to the write request the memory device inputs the first amount of data corresponding to the first block size information.

Abstract: A method of operation of a synchronous memory device having at least one memory section which includes a plurality of memory locations. The method comprises receiving an external clock signal having a fixed frequency, receiving a read request, including addressing information, synchronously with respect to the external clock signal, initiating an internal memory addressing operation, in response to the read request, and outputting data onto the external bus synchronously with respect to the external clock signal. The synchronous memory device may include interface circuitry, coupled to an external bus, to receive a write request packet synchronously with respect to an external clock. The write request packet may include N bits of information and the external bus includes M number of signal lines wherein N is substantially greater than M.

Abstract: A synchronous memory device having a plurality of memory cells and a method of operation thereof. The memory device comprising: receiver circuitry to receive a first external clock signal; and output driver circuitry, to output data after a preprogrammed number of clock cycles of the first external clock signal transpire. The data is output synchronously with respect to the first external clock signal. The method of operation comprises: receiving a request for a read operation; sensing data in a portion of the plurality of sense amplifiers in response to the request for a read operation; and outputting the data after a preprogrammed delay time transpires. The method may further include receiving an external clock signal wherein the preprogrammed time delay is representative of a fixed number of clock cycles of the external clock signal. The data is output synchronously with respect to the first external clock signal.

Abstract: A method of operating a synchronous memory device, wherein the memory device includes a plurality of memory cells and a register for storing an identification value which identifies the memory device on a bus. Block size information is provided to the memory device, wherein the block size information specifies an amount of data to be output onto a bus in response to a read request. The read request is issued to the memory device, and includes identification information, wherein in response to the read request, the memory device determines whether the identification information corresponds to the identification value stored in the register. When the identification information corresponds to the identification value, the memory device outputs an amount of data corresponding to the block size information onto the bus synchronously with respect to at least a first external clock. The memory device may further include a programmable register.

Abstract: The present invention is directed to a synchronous memory device having a memory cell array divided into a plurality of subarrays, including first and second subarrays each having a plurality of subarray sections. The memory device further includes a device identification register to store an identification code to identify the memory device. A first subarray section in the memory device includes a first internal I/O line to access data from a first memory cell location in the first subarray section and a second internal I/O line to access data from a second memory cell location in the first subarray section. A second subarray section in the memory device includes a first internal I/O line to access data from a third memory cell location in the second subarray section and a second internal I/O line to access data from a fourth memory cell location in the second subarray section.

Abstract: A system for use in a computer, the system comprises a memory device and a controller or master to generate a request to provide data. The memory device includes at least one section of memory, having a plurality of memory cells, and a programmable register to store a value which is representative of a number of clock cycles of a first external clock signal to transpire before the memory device outputs data onto the bus in response to the request to provide data. The memory device may further include a plurality of output drivers and a delay lock loop circuitry wherein the delay lock loop circuitry generates a first internal clock signal using the first external clock signal. The plurality of output drivers, in response to the first internal clock signal, output data onto the bus. The plurality of output drivers output data on the bus after the number of clock cycles of the first external clock signal transpire and synchronously with respect to the first external clock signal.

Abstract: A synchronous memory device having at least one memory section which includes a plurality of memory cells. The memory device includes clock receiver circuitry, clock generation circuitry and input receiver circuitry. The clock receiver circuitry receives an external clock signal from an external bus. The clock generation circuitry is coupled to the clock receiver circuitry, and includes a delay locked loop to generate a first internal clock signal. The input receiver circuitry is coupled to the clock generation circuitry and the external bus to sample information from the external bus in response to the first internal clock signal.

Abstract: A memory system having a plurality of memory devices, each having at least one memory array which includes a plurality of memory cells. The memory system comprises a bus, a controller, a first memory device, and a second memory device. The bus includes a plurality of sisal lines coupled to the plurality of memory devices. The bus provides a transaction request including identification information generated by the controller, to the plurality of memory devices. The first and second memory device each include a programmable register, interface circuitry, and comparison circuitry. The interface circuitry of each memory device may store a memory identification value to identify each memory device on the bus. The interface circuitry of each memory device is coupled to the bus to receive a transaction request.