Abstract: High-speed data transfer rates are provided between a central office and customer premise equipment with a multiplexer that is interposed between the central office and the customer premise equipment, and that functions as a remote access node. The multiplexer communicates at high data rates via downstream data links such as twisted-pair conductors between the multiplexer and the customer premise equipment. By positioning the multiplexer physically close to the customer premise equipment, DSL data rates can be achieved. In one application, the multiplexer assigns a variable number of the upstream data links between the central office and the multiplexer on a dynamic, adaptive, and automatic basis to individual ones of the downstream data links. In this way, unused data link capacity of the upstream data links is used to provide high data transmission rates when required between the multiplexer and the central office.

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention.

Abstract: A synchronous semiconductor memory device including a memory cell array and a plurality of input receivers to sample address information synchronously with respect to a clock signal. The address information includes a row address and a column address. The memory device further includes a plurality of sense amplifiers to sense data from a row of the memory cell array, the row of the memory cell array being identified by the row address. Furthermore, the memory device includes a plurality of column decoders coupled to the plurality of sense amplifiers to access, based on the column address, a plurality of data bits of the data sensed by the plurality of sense amplifiers.

Abstract: An enhanced mobile communication device communicates directly with other enhanced mobile communication devices in an ad-hoc mode over a wireless medium. The device transmits and receives packets of digital data. The packets of digital data are such that when transmitted, the probability that they will be received by the other mobile communication devices is increased. The probability is further increased by transmitting the packets a multiple and variable number of times according activity in the wireless medium. Attempts to transmit are made periodically and the period of transmission is adjusted according to activity in the wireless medium. In a transportation application, the packets comprise vehicle traffic congestion update information. The device maintains a traffic database and a map database. Traffic congestion update information is exchanged with other devices.

Abstract: A controller device for controlling a synchronous dynamic random access memory device. The controller device includes output driver circuitry to output block size information to the memory device. The block size information defines an amount of data to be output by the memory device. In addition, the controller device includes input receiver circuitry to receive the amount of data output by the memory device.

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention.

Abstract: An integrated circuit device that includes a clock synchronization circuit. The clock synchronization circuit receives an external clock signal and generates an internal clock signal from the external clock signal using a feedback loop. The internal clock signal is adjusted based on feedback provided via the feedback loop. In addition, the integrated circuit device includes an output circuit. The output circuit includes an output driver to output at least two bits of data in succession during a clock cycle of the external clock signal. The data is output synchronously with respect to the internal clock signal.

Abstract: A faster modem apparatus communicates with customer premise equipment according to a variety of communication protocols. The faster modem apparatus communicates with customer premise equipment comprising an analog soft-modem comprising a codec. A method utilizes an unused portion of the codec operating range to code and decode data signals having frequencies above 4 kHz. The faster modem apparatus also codes and decodes data signals above 4 kHz. The analog soft-modem and the faster modem apparatus transmit and receive coded analog signals at a signal level of greater than −9 dBm. In one embodiment, the faster modem apparatus is also operative to communicate with additional modems such as dial-up modems and DSL modems. In one embodiment, the faster modem apparatus supports simultaneous voice and data communications.

Abstract: In one embodiment, a modular memory device is presented comprising a substrate, a memory array fabricated above the substrate, and first and second circuitry fabricated on the substrate and under the memory array. The first and second circuitry allow the modular memory device to interface with first and second varieties of host devices, respectively. In another embodiment, a modular memory device is presented comprising a substrate, a memory array fabricated above the substrate, memory array support circuitry fabricated on the substrate, and logic circuitry fabricated on the substrate and under the memory array.

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention.

Abstract: A method of operation of a synchronous memory device. The memory device includes an array of dynamic random access memory cells. The method of operation of the memory device includes receiving an external clock signal, and sampling a first operation code synchronously with respect to the external clock signal, the first operation code specifying a write operation. Additionally, the method of operation of the memory device includes sampling data after a number of clock cycles of the external clock signal transpire. The data is sampled in response to the first operation code.

Abstract: An integrated circuit device which includes an array of dynamic memory cells. The integrated circuit device comprises an input receiver to sample an operation code synchronously with respect to a transition of a clock signal, the operation code indicating a read operation. The integrated circuit device also comprises an output driver to output data in response to the operation code, wherein the data is output after a number of clock cycles of the clock signal transpire.

Abstract: A synchronous memory device including an array of memory cells. The memory device includes a plurality of sense amplifiers, coupled to the array of memory cells, to sense data. The memory device further includes input receiver circuitry to sample an operation code synchronously with respect to a transition of an external clock signal. The operation code including precharge information and, in response to the precharge information, the plurality of sense amplifiers are automatically precharged after the data is sensed.

Abstract: A synchronous integrated circuit memory device including an array of memory cells. The memory device includes a clock receiver to receive an external clock signal, and a plurality of sense amplifiers, coupled to the array of memory cells, to sense data. A first portion of the data is output from the memory device in response to a first operation code bit specifying a read operation. In addition, the memory device includes a first input receiver to sample the first operation code bit in response to a first transition of the external clock signal. Furthermore, the memory device includes a second input receiver to sample a second operation code bit in response to the first transition of the external clock signal. The second operation code bit indicates whether precharging the plurality of sense amplifiers occurs automatically after the data has been sensed. Moreover, the memory device includes a plurality of output drivers to output the portion of the data synchronously with respect to the external clock signal.

Abstract: A modular memory device includes a support element, a memory unit comprising a three-dimensional memory array carried by the support element, a device interface unit carried by the support element and coupled with the memory unit, and an electrical connector carried by the support element and coupled with the device interface unit. The memory array is well suited for use as a digital medium storage device for digital media such as digital text, digital music, digital image or images, and digital video. The device interface unit is not required in all cases.

Abstract: A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Abstract: A low-cost memory cell array includes multiple, vertically-stacked layers of memory cells. In one form, each memory cell is characterized by a small cross-sectional area and a read current less than 6.3 microamperes. The resulting memory array has a slow access time and is well-suited for digital media storage, where access time requirements are low and the dramatic cost reductions associated with the disclosed memory arrays are particularly attractive. In another form, each memory cell includes an antifuse layer and diode components, wherein at least one diode component is heavily doped (to a dopant concentration greater than 1019/cm3), and wherein the read current is large (up to 500 mA).

Abstract: A memory device and a method of operation of the memory device. The memory device includes an array of memory cells and a reference voltage input terminal to receive an external reference voltage. In addition, the memory device includes an input receiver, coupled to the reference voltage input terminal, to sample data from an external signal line using the external reference voltage.

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.