Patents by Inventor Michael John Sebastian Smith

Michael John Sebastian Smith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for power management in memory systems
    Patent number: 7590796
    Abstract: A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of physical memory circuits and a system. The interface circuit is operable to interface the physical memory circuits and the system for simulating at least one virtual memory circuit with a first power behavior that is different from a second power behavior of the physical memory circuits.
    Type: Grant
    Filed: September 20, 2006
    Date of Patent: September 15, 2009
    Assignee: MetaRAM, Inc.
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • Power saving system and method for use with a plurality of memory circuits
    Patent number: 7580312
    Abstract: A power saving system and method are provided. In use, at least one of a plurality of memory circuits is identified that is not currently being accessed. In response to the identification of the at least one memory circuit, a power saving operation is initiated in association with the at least one memory circuit.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: August 25, 2009
    Assignee: MetaRAM, Inc.
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • Interface circuit system and method for performing power saving operations during a command-related latency
    Patent number: 7581127
    Abstract: A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing a power management operation in association with at least a portion of the memory circuits. Such power management operation is performed during a latency associated with one or more commands directed to at least a portion of the memory circuits.
    Type: Grant
    Filed: October 20, 2006
    Date of Patent: August 25, 2009
    Assignee: MetaRAM, Inc.
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • Gigabit ethernet adapter supporting the iSCSI and IPSEC protocols
    Patent number: 7535913
    Abstract: The invention is embodied in a gigabit Ethernet adapter. A system according to the invention provides a compact hardware solution to handling high network communication speeds. In addition, the invention adapts to multiple communication protocols via a modular construction and design.
    Type: Grant
    Filed: June 5, 2003
    Date of Patent: May 19, 2009
    Assignee: NVIDIA Corporation
    Inventors: John Shigeto Minami, Robin Yasu Uyeshiro, Michael Ward Johnson, Steve Su, Michael John Sebastian Smith, Addison Kwuanming Chen, Mihir Shaileshbhai Doctor, Daniel Leo Greenfield
  • MEMORY CIRCUIT SYSTEM AND METHOD
    Publication number: 20090024789
    Abstract: A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).
    Type: Application
    Filed: October 30, 2007
    Publication date: January 22, 2009
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • Interface circuit system and method for performing power management operations utilizing power management signals
    Patent number: 7472220
    Abstract: A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for communicating a first number of power management signals to at least a portion of the memory circuits that is different from a second number of power management signals received from the system.
    Type: Grant
    Filed: September 20, 2006
    Date of Patent: December 30, 2008
    Assignee: MetaRAM, Inc.
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • INTERFACE CIRCUIT SYSTEM AND METHOD FOR AUTONOMOUSLY PERFORMING POWER MANAGEMENT OPERATIONS IN CONJUNCTION WITH A PLURALITY OF MEMORY CIRCUITS
    Publication number: 20080239858
    Abstract: A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for autonomously performing a power management operation in association with at least a portion of the memory circuits.
    Type: Application
    Filed: April 29, 2008
    Publication date: October 2, 2008
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • INTERFACE CIRCUIT SYSTEM AND METHOD FOR PERFORMING POWER MANAGEMENT OPERATIONS IN CONJUNCTION WITH ONLY A PORTION OF A MEMORY CIRCUIT
    Publication number: 20080239857
    Abstract: A memory circuit power management system and method are provided. An interface circuit is in communication with a plurality of memory circuits and a system.
    Type: Application
    Filed: April 29, 2008
    Publication date: October 2, 2008
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
    Patent number: 7392338
    Abstract: A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for autonomously performing a power management operation in association with at least a portion of the memory circuits.
    Type: Grant
    Filed: September 20, 2006
    Date of Patent: June 24, 2008
    Assignee: MetaRAM, Inc.
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
    Patent number: 7386656
    Abstract: A memory circuit power management system and method are provided. An interface circuit is in communication with a plurality of memory circuits and a system.
    Type: Grant
    Filed: September 20, 2006
    Date of Patent: June 10, 2008
    Assignee: MetaRAM, Inc.
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • SYSTEM AND METHOD FOR SIMULATING AN ASPECT OF A MEMORY CIRCUIT
    Publication number: 20080133825
    Abstract: A memory subsystem is provided including an interface circuit adapted for coupling with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for emulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. Such aspect includes a signal, a capacity, a timing, and/or a logical interface.
    Type: Application
    Filed: October 30, 2007
    Publication date: June 5, 2008
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • MEMORY DEVICE WITH EMULATED CHARACTERISTICS
    Publication number: 20080126687
    Abstract: A memory subsystem is provided including an interface circuit adapted for communication with a system and a majority of address or control signals of a first number of memory circuits. The interface circuit includes emulation logic for emulating at least one memory circuit of a second number.
    Type: Application
    Filed: October 30, 2007
    Publication date: May 29, 2008
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • MEMORY DEVICE WITH EMULATED CHARACTERISTICS
    Publication number: 20080126689
    Abstract: A memory subsystem is provided including an interface circuit adapted for communication with a system and a majority of address or control signals of a first number of memory circuits. The interface circuit includes emulation logic for emulating at least one memory circuit of a second number.
    Type: Application
    Filed: October 30, 2007
    Publication date: May 29, 2008
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • COMBINED SIGNAL DELAY AND POWER SAVING SYSTEM AND METHOD FOR USE WITH A PLURALITY OF MEMORY CIRCUITS
    Publication number: 20080123459
    Abstract: A system and method are provided. In use, at least one of a plurality of memory circuits is identified. In association with the at least one memory circuit, a power saving operation is performed and the communication of a signal thereto is delayed.
    Type: Application
    Filed: October 26, 2006
    Publication date: May 29, 2008
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • MEMORY DEVICE WITH EMULATED CHARACTERISTICS
    Publication number: 20080126688
    Abstract: A memory subsystem is provided including an interface circuit adapted for communication with a system and a majority of address or control signals of a first number of memory circuits. The interface circuit includes emulation logic for emulating at least one memory circuit of a second number.
    Type: Application
    Filed: October 30, 2007
    Publication date: May 29, 2008
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • MEMORY DEVICE WITH EMULATED CHARACTERISTICS
    Publication number: 20080126692
    Abstract: A memory subsystem is provided including an interface circuit adapted for communication with a system and a majority of address or control signals of a first number of memory circuits. The interface circuit includes emulation logic for emulating at least one memory circuit of a second number.
    Type: Application
    Filed: October 30, 2007
    Publication date: May 29, 2008
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • SYSTEM AND METHOD FOR REDUCING COMMAND SCHEDULING CONSTRAINTS OF MEMORY CIRCUITS
    Publication number: 20080120443
    Abstract: A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constraints of the memory circuits.
    Type: Application
    Filed: October 30, 2007
    Publication date: May 22, 2008
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
  • SYSTEM AND METHOD FOR ADJUSTING THE TIMING OF SIGNALS ASSOCIATED WITH A MEMORY SYSTEM
    Publication number: 20080115006
    Abstract: A system and method are provided for adjusting the timing of signals associated with a memory system. A memory controller is provided. Additionally, at least one memory module is provided. Further, at least one interface circuit is provided, the interface circuit capable of adjusting timing of signals associated with one or more of the memory controller and the at least one memory module.
    Type: Application
    Filed: November 13, 2007
    Publication date: May 15, 2008
    Inventors: Michael John Sebastian Smith, Daniel L. Rosenband, David T. Wang, Suresh Natarajan Rajan
  • APPARATUS AND METHOD FOR POWER MANAGEMENT OF MEMORY CIRCUITS BY A SYSTEM OR COMPONENT THEREOF
    Publication number: 20080082763
    Abstract: An apparatus and method are provided for communicating with a plurality of physical memory circuits. In use, at least one virtual memory circuit is simulated where at least one aspect (e.g. power-related aspect, etc.) of such virtual memory circuit(s) is different from at least one aspect of at least one of the physical memory circuits. Further, in various embodiments, such simulation may be carried out by a system (or component thereof), an interface circuit, etc.
    Type: Application
    Filed: October 2, 2006
    Publication date: April 3, 2008
    Inventors: Suresh Natarajan Rajan, Michael John Sebastian Smith, David T. Wang
  • SYSTEM AND METHOD FOR SIMULATING AN ASPECT OF A MEMORY CIRCUIT
    Publication number: 20080062773
    Abstract: A memory subsystem is provided including an interface circuit adapted for coupling with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for emulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. Such aspect includes a signal, a capacity, a timing, and/or a logical interface.
    Type: Application
    Filed: June 12, 2007
    Publication date: March 13, 2008
    Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber