Patents by Inventor Michael Sadd

Michael Sadd has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6686245
    Abstract: A semiconductor fabrication process and structure in which a semiconductor channel structure (140) having first and second major surfaces perpendicular to a semiconductor substrate (102) is formed overlying and electrically isolated from the substrate (102). First and second gate dielectrics (120, 142) are formed on the channel structure's first and second major surfaces respectively. First and second gate dielectrics (120, 142) differ in at least one characteristic. First and second gate electrodes (116, 152) are formed in contact with the first and second gate dielectrics (120, 142) respectively. The first and second gate electrodes (116, 152) differ in at least one characteristic. First and second gate dielectrics (120, 142) may have different dielectric constants while first and second gate electrodes (116, 152) may have different doping and conducting properties.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: February 3, 2004
    Assignee: Motorola, Inc.
    Inventors: Leo Mathew, Michael Sadd
  • Publication number: 20030151077
    Abstract: A vertical double gate semiconductor device (10) having separate, non-contiguous gate electrode regions (62, 64) is described. The separate gate electrode regions can be formed by depositing a gate electrode material (28) and anisotropically etching, planarizing or etching back the gate electrode material to form the separate gate electrode regions on either side of the vertical double gate semiconductor device. One (66) or two (68, 70) contacts are formed over the separate gate electrode regions that may or may not be electrically isolated from each other. If formed from polysilicon, the separate gate electrode regions are doped. In one embodiment, the separate gate electrode regions are doped the same conductivity. In another embodiment, an asymmetrical semiconductor device is formed by doping one separate gate electrode region n-type and the other separate gate electrode region p-type.
    Type: Application
    Filed: February 13, 2002
    Publication date: August 14, 2003
    Inventors: Leo Mathew, Bich-Yen Nguyen, Michael Sadd, Bruce E. White
  • Patent number: 6444545
    Abstract: A semiconductor device structure for storing charge has a silicon nitride layer, in which a plurality of nanoclusters are sandwiched between oxide layers. The nanoclusters and the silicon nitride make up a storage region, which is particularly useful in non-volatile memories. The nanoclusters provide a repository for holes or electrons that jump from trap to trap in the silicon nitride when the silicon nitride is heated. This results in much of the charge, which would normally leak off from the silicon nitride at high temperatures, remaining in the storage region due to trapping in the nanoclusters. The silicon nitride layer with nanoclusters therein is formed by depositing a silicon nitride layer, then nanoclusters, and then another silicon nitride layer or by depositing a silicon-rich silicon nitride layer and subsequent heating to cause it to transform to a regular silicon nitride layer with silicon nanoclusters therein.
    Type: Grant
    Filed: December 19, 2000
    Date of Patent: September 3, 2002
    Assignee: Motorola, Inc.
    Inventors: Michael A. Sadd, Sucharita Madhukar, Frank Kelsey Baker
  • Patent number: 6413819
    Abstract: A semiconductor device that includes a floating gate made up of a plurality of pre-formed isolated storage elements (18) and a method for making such a device is presented. The device is formed by first providing a semiconductor layer (12) upon which a first gate insulator (14) is formed. A plurality of pre-fabricated isolated storage elements (18) is then deposited on the first gate insulator (14). This deposition step may be accomplished by immersion in a colloidal solution (16) that includes a solvent and pre-fabricated isolated storage elements (18). Once deposited, the solvent of the solution (16) can be removed, leaving the pre-fabricated isolated storage elements (18) deposited on the first gate insulator (14). After depositing the pre-fabricated isolated storage elements (18), a second gate insulator (20) is formed over the pre-fabricated isolated storage elements (18).
    Type: Grant
    Filed: June 16, 2000
    Date of Patent: July 2, 2002
    Assignee: Motorola, Inc.
    Inventors: Sufi Zafar, Ramachandran Muralidhar, Bich-Yen Nguyen, Sucharita Madhukar, Daniel T. Pham, Michael A. Sadd, Chitra K. Subramanian
  • Publication number: 20020076850
    Abstract: A semiconductor device structure for storing charge has a silicon nitride layer, in which a plurality of nanoclusters are sandwiched between oxide layers. The nanoclusters and the silicon nitride make up a storage region, which is particularly useful in non-volatile memories. The nanoclusters provide a repository for holes or electrons that jump from trap to trap in the silicon nitride when the silicon nitride is heated. This results in much of the charge, which would normally leak off from the silicon nitride at high temperatures, remaining in the storage region due to trapping in the nanoclusters. The silicon nitride layer with nanoclusters therein is formed by depositing a silicon nitride layer, then nanoclusters, and then another silicon nitride layer or by depositing a silicon-rich silicon nitride layer and subsequent heating to cause it to transform to a regular silicon nitride layer with silicon nanoclusters therein.
    Type: Application
    Filed: December 19, 2000
    Publication date: June 20, 2002
    Inventors: Michael A. Sadd, Sucharita Madhukar, Frank Kelsey Baker
  • Patent number: 6297095
    Abstract: A semiconductor memory device with a floating gate that includes a plurality of nanoclusters (21) and techniques useful in the manufacturing of such a device are presented. The device is formed by first providing a semiconductor substrate (12) upon which a tunnel dielectric layer (14) is formed. A plurality of nanoclusters (19) is then grown on the tunnel dielectric layer (14). After growth of the nanoclusters (21), a control dielectric layer (20) is formed over the nanoclusters (21). In order to prevent oxidation of the formed nanoclusters (21), the nanoclusters (21) may be encapsulated using various techniques prior to formation of the control dielectric layer (20). A gate electrode (24) is then formed over the control dielectric (20), and portions of the control dielectric, the plurality of nanoclusters, and the gate dielectric that do not underlie the gate electrode are selectively removed.
    Type: Grant
    Filed: June 16, 2000
    Date of Patent: October 2, 2001
    Assignee: Motorola, Inc.
    Inventors: Ramachandran Muralidhar, Chitra K. Subramanian, Sucharita Madhukar, Bruce E. White, Michael A. Sadd, Sufi Zafar, David L. O'Meara, Bich-Yen Nguyen