Patents by Inventor Michael Thomas Benhase

Michael Thomas Benhase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080055644
    Abstract: Provided are a method, system, and article of manufacture for validating stored copies of data images to load into memory. An image of data is maintained in a memory, wherein the image in the memory includes a generation number. The image in the memory is written to at least two copies of the image to storage locations in response to a first event, wherein the generation number for the image in the memory is stored in the storage locations having the copies of the image. A check generation number is stored in a storage location. The image is loaded from at least one of the copies of the image in one of the storage locations to the memory in response to a second event. The generation number for the image loaded into the memory. The check generation number is incremented in response to the second event. The generation numbers for the copies of the image in the storage locations and the check generation number are used to validate the copies of the image.
    Type: Application
    Filed: September 1, 2006
    Publication date: March 6, 2008
    Applicant: International Business Machines Corporation
    Inventors: Said Abdullah Ahmad, Michael Thomas Benhase, David Frank Mannenbach, Tim Stephen Vande Zande
  • Patent number: 7337277
    Abstract: An apparatus, system, and method are disclosed for flushing cache data in a cache system. The apparatus includes a zero module and a flush module. The zero module executes an internal processor instruction to zero out a zero memory segment of a nonvolatile memory and a processor cache in response to a loss of primary power to the processor cache. The flush module flushes modified data from an address in the processor cache to a flush memory segment of the nonvolatile memory before the zero module puts a zero in the address. Advantageously, the zero memory segment is reserved within the memory and used to zero out the processor cache, effectively flushing the existing data from the processor cache to a flush memory segment of the memory.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: February 26, 2008
    Assignee: International Business Machines Corporation
    Inventors: Michael Thomas Benhase, Stephen LaRoux Blinick, Andrew Dale Walls
  • Publication number: 20080021853
    Abstract: Provided are a method, system and program for using multiple data structures to manage data in cache. A plurality of data structures each have entries identifying data from a first computer readable medium added to a second computer readable medium. A request is received for data in the first computer readable medium. A determination is made as to whether there is an entry for the requested data in one of the data structures. The requested data is retrieved from the first computer readable medium to store in the second computer readable medium in response to determining that there is no entry for the requested data in one of the data structures. One of the data structures is selected in response to determining that there is no entry for the requested data in one of the data structures and an entry for the retrieved data is added to the selected data structure.
    Type: Application
    Filed: July 20, 2006
    Publication date: January 24, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dharmendra Shantilal Modha, Binny Sher Gill, Michael Thomas Benhase, Joseph Smith Hyde
  • Patent number: 7305526
    Abstract: Provided are a method, system, and program for transferring data directed to virtual memory addresses to a device memory. Indicator bits are set for ranges of device memory addresses in a device accessible over an Input/Output (I/O) bus indicating whether gathering is enabled for the device memory address ranges. Transfer operations are processed to transfer data to contiguous device memory addresses in the device. A determination is made as to whether the indicator bits for the contiguous device memory addresses indicate that gathering is enabled. A single bus I/O transaction is generated to transfer data for the contiguous device memory addresses over the I/O bus in response to determining that the indicator bits for the contiguous device memory addresses indicate that gathering is enabled.
    Type: Grant
    Filed: November 5, 2004
    Date of Patent: December 4, 2007
    Assignee: International Business Machines Corporation
    Inventors: Michael Thomas Benhase, Robert Alan Cargnoni, James Stephen Fields, Jr., Michael John Mayfield, Bruce Mealey
  • Patent number: 7251753
    Abstract: An apparatus, method, and system associates an identifier with a data packet. The identifier uniquely identifies a communication module, such as a host interface card, within a data storage system. In operation, a computer host sends a data packet to a server. The communication module receives the data packet and associates an identifier, unique to the communication module, with the data packet. The data packet is stored in a disk array, such as a Redundant Array of Independent Disks (RAID) system. When the computer host later requests the stored data packet, a validation module, which may be implemented within a PCI adapter such as a host interface card, retrieves the data packet and determines whether the data packet is corrupt. If the data packet is corrupt, the validation module identifies which host interface card corrupted the data with the use of the unique identifier associated with the data packet. The faulty communication module may then be removed from operation in the data storage system.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: July 31, 2007
    Assignee: International Business Machines Corporation
    Inventors: Michael Thomas Benhase, Susan Kay Candelaria, Paul Matthew Richards, Brian Anthony Rinaldi
  • Patent number: 7219267
    Abstract: Disclosed is a technique for fault isolation. A first error check is performed on a block of data in storage to determine whether the block of data was corrupted after the block of data was transferred from memory to the storage. When the first error check indicates that the block of data was corrupted, a second error check is performed using the block of data in the memory to determine whether the block of data was corrupted before being transferred from the memory. When the second error check indicates that the block of data was corrupted before being transferred from the memory, it is determined that the block of data was corrupted before being stored in the memory. When the second error check indicates that the block of data was corrupted after being transferred from the memory, it is determined that the block of data was corrupted by at least one of the memory or a formatter that performed the transfer.
    Type: Grant
    Filed: January 7, 2004
    Date of Patent: May 15, 2007
    Assignee: International Business Machines Corporation
    Inventors: Kevin Lee Gibble, James Chien-Chiung Chen, Michael Thomas Benhase, Minh-Ngoc Le Huynh
  • Patent number: 7191465
    Abstract: Provided are a method, system and program for processing complexes to access shared devices. A lock to a plurality of shared devices is maintained and accessible to a first and second processing systems. The first processing complex determines a first delay time and the second processing complex determines a second delay time. The first processing complex issues a request for the lock in response to expiration of the first delay time and the second processing complex issues a request for the lock in response to expiration of the second delay time.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: March 13, 2007
    Assignee: International Business Machines Corporation
    Inventors: Michael Thomas Benhase, John Norbert McCauley, Brian Anthony Rinaldi, Micah Robison, Todd Charles Sorenson
  • Patent number: 7178147
    Abstract: Provided is a method, system, and program for allocating processor resources to a first and second types of tasks. An allocation of processor resources to the first and second types of tasks is indicated. Data is gathered indicating a first workload level for the first type of tasks and a second workload level for the second type of tasks. A determination is made of a change to the indicated allocation of processor resources to the first and second types of tasks based on at least one of the first workload level and second workload level data. Tasks of the first type are dispatched to the processor resources allocated to the first type and tasks of the second type are dispatched to the processor resources allocated to the second type.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: February 13, 2007
    Assignee: International Business Machines Corporation
    Inventors: Michael Thomas Benhase, YuCheng Hsu
  • Patent number: 7171610
    Abstract: Provided are a method, system, and an article of manufacture for preventing data loss. Modified data is stored in a volatile storage. The stored modified data is copied onto a non-volatile storage. A determination is made as to whether the non-volatile storage should be checked for errors. In certain implementations, on determining that the nonvolatile storage should be checked for errors the non-volatile storage is checked for errors. If on checking the non-volatile storage is found to have an error, an indication of the error is provided.
    Type: Grant
    Filed: June 12, 2002
    Date of Patent: January 30, 2007
    Assignee: International Business Machines Corporation
    Inventors: Kevin John Ash, Michael Thomas Benhase, Carol Santich Mellgren, Brian Anthony Rinaldi, Kenneth Wayne Todd
  • Patent number: 7130929
    Abstract: A method to simultaneously configure a plurality of adapters disposed within a computer system, where that computer system includes one or more external computers, and/or one or more data input devices, and/or one or more data output devices, and/or one or more data storage devices. A computer system which includes a computer useable medium having computer readable program code disposed therein to implement Applicants' method to simultaneously configure a plurality of adapters disposed within said computer system. A computer program product usable with a programmable computer processor having computer readable program code embodied therein for simultaneously configuring a plurality of adapters disposed within a computer system.
    Type: Grant
    Filed: July 25, 2001
    Date of Patent: October 31, 2006
    Assignee: International Business Machines Corporation
    Inventors: Michael Thomas Benhase, Brian Jeffrey Corcoran, Matthew Joseph Kalos
  • Patent number: 7107400
    Abstract: A process, apparatus, and system for evaluating a projected cache size implement and manage one or more projected cache lists that each contains directory entries corresponding to a projected cache size. The projected cache size may be either smaller or larger than the actual size of a cache installed in a computer system. Using the projected cache list entries, performance statistics such as cache hit ratio and average access time are tracked for each list. The process, apparatus, and system may calculate performance parameters that describe the performance specific to the actual cache list and each projected cache list. The resulting performance statistics may be used to formulate an optimization parameter to be communicated to a user or an administrator application.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: September 12, 2006
    Assignee: International Business Machines Corporation
    Inventors: Michael Thomas Benhase, Thomas Charles Jarvis, Robert John Kolvick, Jr.
  • Patent number: 7051223
    Abstract: An apparatus for limiting volatile computer memory based on available energy in an auxiliary power source comprises an energy monitor module configured to determine an amount of available energy in the auxiliary power source. Also provided is a memory status module configured to determine an amount of volatile computer memory allocated for use in a computer and a memory adjustment module configured to adjust the amount of volatile computer memory allocated for use in the computer based on the amount of available energy in the auxiliary power source.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: May 23, 2006
    Assignee: International Business Madnine Corporation
    Inventors: Gary William Batchelor, Michael Thomas Benhase, Enrique Garcia, Carl Evan Jones, Trung Le
  • Publication number: 20060107005
    Abstract: An apparatus, system, and method are disclosed for copying data from a volatile memory device to a plurality of persistent storage devices in response to a loss of primary power. The apparatus includes a section module, a stripe module, and a write module. The section module sections a data image of a write cache into a plurality of data blocks. The stripe module establishes a plurality of data stripes from the plurality of data blocks. The write module writes in parallel each of the plurality of data stripes to a corresponding plurality of unique, persistent data storage devices in response to a loss of line power to the write cache. Advantageously, the apparatus quickly copies the write data from the write cache to a persistent memory device in a relatively short period of time, decreasing the dependence on significant batteries to back up the volatile memory device.
    Type: Application
    Filed: November 18, 2004
    Publication date: May 18, 2006
    Inventors: Herve Gilbert Philippe Andre, Michael Thomas Benhase, Yu-Cheng Hsu, David Frank Mannenbach
  • Patent number: 6988171
    Abstract: Disclosed is a method, system, and article of manufacture for processing modified meta data for data recovery operations. The meta data provides information on user data maintained in a storage device. The system determines whether meta data tracks maintained in a cache were modified and indicates in a non-volatile memory that the determined meta data tracks were modified. Data recovery operations may be initiated as a result of a system failure, such as a warmstart or coldstart recovery. During such data recovery operations, the system processes the non-volatile memory and the indications of modified meta data tracks therein to rebuild lost meta data tracks in the cache.
    Type: Grant
    Filed: May 9, 2002
    Date of Patent: January 17, 2006
    Assignee: International Business Machines Corporation
    Inventors: Brent Cameron Beardsley, Michael Thomas Benhase, Douglas A. Martin, Robert Louis Morton, Kenneth Wayne Todd
  • Patent number: 6981102
    Abstract: Disclosed is a method, system, and article of manufacture for managing meta data. The meta data provides information on data maintained in a storage device. The system receives a request for meta data from a process and determines whether the requested meta data is in cache. After determining that the requested meta data is not in cache, the system determines whether there are a sufficient number of allocatable segments in cache to stage in the meta data and allocates segments in cache to store the meta data after determining that there are enough allocatable segments in cache. The system stages the requested meta data into the allocated segments. Alternatively, after determining that the requested meta data is in cache, the system determines whether a second process has exclusive access to the meta data in cache. After determining that the second process does not have exclusive access, the system indicates to the first process that access to the meta data is permitted.
    Type: Grant
    Filed: October 11, 2002
    Date of Patent: December 27, 2005
    Assignee: International Business Machines Corporation
    Inventors: Brent Cameron Beardsley, Michael Thomas Benhase, Douglas A. Martin, Robert Louis Morton, Kenneth Wayne Todd
  • Publication number: 20040205317
    Abstract: A method, apparatus and program storage device for providing data integrity using check data and other metadata on a formatted storage medium.
    Type: Application
    Filed: April 8, 2003
    Publication date: October 14, 2004
    Applicant: International Business Machines Corporation
    Inventors: Andrew Dale Walls, Michael Thomas Benhase, Carl Evan Jones, John Charles Elliott, Carol Spanel, Lih-Chung Kuo, William Garrett Verdoorn
  • Publication number: 20040193801
    Abstract: A process, apparatus, and system for evaluating a projected cache size implement and manage one or more projected cache lists that each contains directory entries corresponding to a projected cache size. The projected cache size may be either smaller or larger than the actual size of a cache installed in a computer system. Using the projected cache list entries, performance statistics such as cache hit ratio and average access time are tracked for each list. The process, apparatus, and system may calculate performance parameters that describe the performance specific to the actual cache list and each projected cache list. The resulting performance statistics may be used to formulate an optimization parameter to be communicated to a user or an administrator application.
    Type: Application
    Filed: March 31, 2003
    Publication date: September 30, 2004
    Inventors: Michael Thomas Benhase, Thomas Charles Jarvis, Robert John Kolvick
  • Patent number: 6785771
    Abstract: Provided is a method, system, and program for destaging data from a first computer readable medium to a second computer readable medium. A list of entries indicating data blocks in the first computer readable medium is scanned. For each entry scanned, a determination is made as to whether the data block indicated in the scanned entry satisfies a criteria. If the data block indicated in the scanned entry satisfies the criteria, then a destage operation is called to destage the data block in the scanned entry from the first computer readable medium to the second computer readable medium. If the called destage operation is not initiated, then the scanned entry is removed from the cache list. The removed scanned entry is added to one destage wait list. During one destage operation, data blocks indicated in entries in the destage wait list are destaged.
    Type: Grant
    Filed: December 4, 2001
    Date of Patent: August 31, 2004
    Assignee: International Business Machines Corporation
    Inventors: Kevin John Ash, Brent Cameron Beardsley, Michael Thomas Benhase, Joseph Smith Hyde, II, Thomas Charles Jarvis, Steven Robert Lowe, David Frank Mannenbach
  • Publication number: 20040158605
    Abstract: A network domain includes a plurality of agents and a domain server, the domain server operable for automatically transmitting messages to the agents to reset the agents upon the occurrence of a critical event. Upon receipt of a restart command, each agent terminates executing processes and then restarts processes.
    Type: Application
    Filed: February 10, 2003
    Publication date: August 12, 2004
    Applicant: International Business Machines Corporation
    Inventors: Linda Van Patten Benhase, Michael Thomas Benhase, Stella Chan, John Richard Paveza, Richard Anthony Ripberger, Michael Liang Tan, Yan Xu
  • Patent number: 6775738
    Abstract: Provided is a method, system, and program for caching updates to one target storage device in a first and second memories, wherein the target storage device is one of a plurality of storage devices. A determination is made of an allocation of available space in the second memory to the storage devices, wherein a total of the allocation of the available space to all the storage devices exceeds one hundred percent of the available space in the second memory. An update to one target storage device is received and then a determination is made as to whether adding the update to the second memory will exceed the allocation of available space for the target storage device in the second memory. One copy of the update is written to the second memory if adding the update to the second memory will not exceed the allocation of available space for the target storage device.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: August 10, 2004
    Assignee: International Business Machines Corporation
    Inventors: Kevin John Ash, Brent Cameron Beardsley, Michael Thomas Benhase