Patents by Inventor Michael Treu
Michael Treu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160155861Abstract: A method of manufacturing a device comprises depositing one or more metallization layers to a substrate, locally heating an area of the one or more metallization layers to obtain a substrate/metallization-layer compound or a metallization-layer compound, the compound comprising an etch-selectivity toward an etching medium which is different to that of the one or more metallization layers outside the area, and removing the one or more metallization layers in the area or outside the area, depending on the etching selectivity in the area or outside the area, by etching with the etching medium to form the device.Type: ApplicationFiled: February 5, 2016Publication date: June 2, 2016Inventors: Roland Rupp, Stefan Woehlert, Thomas Gutt, Michael Treu
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Publication number: 20160064504Abstract: A method of manufacturing a device comprises depositing one or more metallization layers to a substrate, locally heating an area of the one or more metallization layers to obtain a substrate/metallization-layer compound or a metallization-layer compound, the compound comprising an etch-selectivity toward an etching medium which is different to that of the one or more metallization layers outside the area, and removing the one or more metallization layers in the area or outside the area, depending on the etching selectivity in the area or outside the area, by etching with the etching medium to form the device.Type: ApplicationFiled: November 6, 2015Publication date: March 3, 2016Inventors: Roland Rupp, Stefan Woehlert, Thomas Gutt, Michael Treu
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Patent number: 9263443Abstract: A semiconductor device includes a first semiconductor die including a normally-off transistor and a second semiconductor die including a plurality of transistor cells of a normally-on GaN HEMT. One of a source terminal and a drain terminal of the normally-off transistor is electrically coupled to a gate terminal of the normally-on GaN HEMT, and the other one of the source terminal and the drain terminal of the normally-off transistor is electrically coupled to one of a source terminal and a drain terminal of the normally-on GaN HEMT. The second semiconductor die further includes a gate resistor electrically coupled between the gate terminal of the normally-off transistor and respective gates of the plurality of transistor cells, and a voltage clamping element electrically coupled between the gate terminal and one of the source terminal and the drain terminal of the normally-on GaN HEMT.Type: GrantFiled: August 9, 2013Date of Patent: February 16, 2016Assignee: Infineon Technologies Austria AGInventors: Michael Treu, Ralf Siemieniec
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Patent number: 9209281Abstract: A method of manufacturing a device comprises depositing one or more metallization layers to a substrate, locally heating an area of the one or more metallization layers to obtain a substrate/metallization-layer compound or a metallization-layer compound, the compound comprising an etch-selectivity toward an etching medium which is different to that of the one or more metallization layers outside the area, and removing the one or more metallization layers in the area or outside the area, depending on the etching selectivity in the area or outside the area, by etching with the etching medium to form the device.Type: GrantFiled: April 23, 2007Date of Patent: December 8, 2015Assignee: Infineon Technologies AGInventors: Roland Rupp, Stefan Woehlert, Thomas Gutt, Michael Treu
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Publication number: 20150041915Abstract: A semiconductor device arrangement includes a first semiconductor device having a load path and a plurality of second semiconductor devices, each having a load path between a first and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices, and one of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. Each of the second semiconductor devices has at least one device characteristic. At least one device characteristic of at least one of the second semiconductor devices is different from the corresponding device characteristic of others of the second semiconductor devices.Type: ApplicationFiled: January 30, 2013Publication date: February 12, 2015Inventors: Rolf Weis, Michael Treu, Gerald Deboy, Armin Willmeroth, Hans Weber
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Publication number: 20150041831Abstract: Production of an integrated circuit including an electrical contact on SiC is disclosed. One embodiment provides for production of an electrical contact on an SiC substrate, in which a conductive contact is produced on a boundary surface of the SiC substrate by irradiation and absorption of a laser pulse on an SiC substrate.Type: ApplicationFiled: October 28, 2014Publication date: February 12, 2015Inventors: Roland Rupp, Thomas Gutt, Michael Treu
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Patent number: 8895422Abstract: Production of an integrated circuit including an electrical contact on SiC is disclosed. One embodiment provides for production of an electrical contact on an SiC substrate, in which a conductive contact is produced on a boundary surface of the SiC substrate by irradiation and absorption of a laser pulse on an SiC substrate.Type: GrantFiled: March 14, 2013Date of Patent: November 25, 2014Assignee: Infineon Technologies Austria AGInventors: Roland Rupp, Thomas Gutt, Michael Treu
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Patent number: 8866253Abstract: A semiconductor device arrangement includes a first semiconductor device having a load path and a plurality of second semiconductor devices, each having a load path between a first and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices, and one of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. Each of the second semiconductor devices has at least one device characteristic. At least one device characteristic of at least one of the second semiconductor devices is different from the corresponding device characteristic of others of the second semiconductor devices.Type: GrantFiled: January 31, 2012Date of Patent: October 21, 2014Assignee: Infineon Technologies Dresden GmbHInventors: Rolf Weis, Gerald Deboy, Michael Treu, Armin Willmeroth, Hans Weber
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Publication number: 20140264577Abstract: A transistor device includes at least one first type transistor cell including a drift region, a source region, a body region arranged between the source region and the drift region, a drain region, a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a field electrode adjacent the drift region and dielectrically insulated from the drift region by a field electrode dielectric. A gate terminal is coupled to the gate electrode, a source terminal is coupled to the source region, and a control terminal is configured to receive a control signal. A variable resistor is connected between the field electrode and the gate terminal or the source terminal. The variable resistor includes a variable resistance configured to be adjusted by the control signal received at the control terminal.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: Walter Rieger, Hans Weber, Michael Treu, Gerhard Nöbauer, Martin Pölzl, Martin Vielemeyer, Franz Hirler
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Patent number: 8803205Abstract: A semiconductor device includes a gate terminal, at least one control terminal and first and second load terminals and at least one device cell. The at least one device cell includes a MOSFET device having a load path and a control terminal, the control terminal coupled to the gate terminal and a JFET device having a load path and a control terminal, the load path connected in series with the load path of the MOSFET device between the load terminals. The at least one device cell further includes a first coupling transistor having a load path and a control terminal, the load path coupled between the control terminal of the JFET device and one of the source terminal and the gate terminal, and the control terminal coupled to the at least one control terminal of the transistor device.Type: GrantFiled: May 31, 2012Date of Patent: August 12, 2014Assignee: Infineon Technologies Austria AGInventors: Armin Willmeroth, Franz Hirler, Hans Weber, Michael Treu
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Patent number: 8618644Abstract: An electronic device and manufacturing thereof. One embodiment provides a semiconductor chip having a control electrode and a first load electrode on a first surface and a second load electrode on a second surface. A first lead is electrically coupled to the control electrode. A second lead is electrically coupled to the first load electrode. A third lead is electrically coupled to the first load electrode, the third lead being separate from the second lead. A fourth lead is electrically coupled to the second load electrode, the second and third leads being arranged between the first and fourth leads.Type: GrantFiled: August 27, 2012Date of Patent: December 31, 2013Assignee: Infineon Technologies AGInventors: Ralf Otremba, Marco Seibt, Uwe Kirchner, Wolfgang Peinhopf, Michael Treu, Andreas Schloegl, Mario Veldvoss
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Publication number: 20130320354Abstract: A semiconductor device includes a first semiconductor die including a normally-off transistor and a second semiconductor die including a plurality of transistor cells of a normally-on GaN HEMT. One of a source terminal and a drain terminal of the normally-off transistor is electrically coupled to a gate terminal of the normally-on GaN HEMT, and the other one of the source terminal and the drain terminal of the normally-off transistor is electrically coupled to one of a source terminal and a drain terminal of the normally-on GaN HEMT. The second semiconductor die further includes a gate resistor electrically coupled between the gate terminal of the normally-off transistor and respective gates of the plurality of transistor cells, and a voltage clamping element electrically coupled between the gate terminal and one of the source terminal and the drain terminal of the normally-on GaN HEMT.Type: ApplicationFiled: August 9, 2013Publication date: December 5, 2013Inventors: Michael Treu, Ralf Siemieniec
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Patent number: 8530904Abstract: A semiconductor device is disclosed. One embodiment includes a first semiconductor die having a normally-off transistor. In a second semiconductor die a plurality of transistor cells of a normally-on transistor are formed, wherein one of a source terminal/drain terminal of the normally-on transistor is electrically coupled to a gate terminal of the normally-on transistor and the other one the source terminal/drain terminal of the normally-off transistor is electrically coupled to one of a source terminal/drain terminal of the normally-on transistor. The second semiconductor die includes a gate resistor electrically coupled between the gate terminal of the normally-off transistor and respective gates of the plurality of transistor cells. A voltage clamping element is electrically coupled between the gate terminal and the one of the source terminal/drain terminal of the normally-on transistor.Type: GrantFiled: March 19, 2010Date of Patent: September 10, 2013Assignee: Infineon Technologies Austria AGInventors: Michael Treu, Ralf Siemieniec
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Patent number: 8525254Abstract: A semiconductor device as described herein includes a silicon carbide semiconductor body. A trench extends into the silicon carbide semiconductor body at a first surface. A gate dielectric and a gate electrode are formed within the trench. A body zone of a first conductivity type adjoins to a sidewall of the trench, the body zone being electrically coupled to a contact via a body contact zone including a higher maximum concentration of dopants than the body zone. An extension zone of the first conductivity type is electrically coupled to the contact via the body zone, wherein a maximum concentration of dopants of the extension zone along a vertical direction perpendicular to the first surface is higher than the maximum concentration of dopants of the body zone along the vertical direction. A distance between the first surface and a bottom side of the extension zone is larger than the distance between the first surface and the bottom side of the trench.Type: GrantFiled: August 12, 2010Date of Patent: September 3, 2013Assignee: Infineon Technologies Austria AGInventors: Michael Treu, Ralf Siemieniec
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Publication number: 20130193525Abstract: A semiconductor device arrangement includes a first semiconductor device having a load path and a plurality of second semiconductor devices, each having a load path between a first and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices, and one of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. Each of the second semiconductor devices has at least one device characteristic. At least one device characteristic of at least one of the second semiconductor devices is different from the corresponding device characteristic of others of the second semiconductor devices.Type: ApplicationFiled: January 31, 2012Publication date: August 1, 2013Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Rolf Weis, Gerald Deboy, Michael Treu, Armin Willmeroth, Hans Weber
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Patent number: 8492771Abstract: A semiconductor device includes a first semiconductor substrate of a first band-gap material and a second semiconductor substrate of a second band-gap material. The second band-gap material has a lower band-gap than the first band-gap material. A heterojunction is formed between the first semiconductor substrate and the second semiconductor substrate substantially in a first plane. The semiconductor device further includes, in a cross-section which is perpendicular to the first plane, a first semiconductor region of a first conductivity type and a second semiconductor region of the first conductivity type both of which extend from the second semiconductor substrate at least partially into the first semiconductor substrate.Type: GrantFiled: September 27, 2007Date of Patent: July 23, 2013Assignee: Infineon Technologies Austria AGInventors: Michael Rüb, Michael Treu, Armin Willmeroth, Franz Hirler
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Patent number: 8450196Abstract: Production of an integrated circuit including an electrical contact on SiC is disclosed. One embodiment provides for production of an electrical contact on an SiC substrate, in which a conductive contact is produced on a boundary surface of the SiC substrate by irradiation and absorption of a laser pulse on an SiC substrate.Type: GrantFiled: October 25, 2007Date of Patent: May 28, 2013Assignee: Infineon Technologies Austria AGInventors: Roland Rupp, Thomas Gutt, Michael Treu
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Patent number: 8421147Abstract: A MOS transistor having an increased gate-drain capacitance is described. One embodiment provides a drift zone of a first conduction type. At least one transistor cell has a body zone, a source zone separated from the drift zone by the body zone, and a gate electrode, which is arranged adjacent to the body zone and which is dielectrically insulated from the body zone by a gate dielectric. At least one compensation zone of the first conduction type is arranged in the drift zone. At least one feedback electrode is arranged at a distance from the body zone, which is dielectrically insulated from the drift zone by a feedback dielectric and which is electrically conductively connected to the gate electrode.Type: GrantFiled: December 22, 2010Date of Patent: April 16, 2013Assignee: Infineon Technologies Austria AGInventors: Armin Willmeroth, Michael Treu
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Publication number: 20120319109Abstract: An electronic device and manufacturing thereof. One embodiment provides a semiconductor chip having a control electrode and a first load electrode on a first surface and a second load electrode on a second surface. A first lead is electrically coupled to the control electrode. A second lead is electrically coupled to the first load electrode. A third lead is electrically coupled to the first load electrode, the third lead being separate from the second lead. A fourth lead is electrically coupled to the second load electrode, the second and third leads being arranged between the first and fourth leads.Type: ApplicationFiled: August 27, 2012Publication date: December 20, 2012Applicant: INFINEON TECHNOLOGIES AGInventors: Ralf Otremba, Marco Seibt, Uwe Kirchner, Wolfgang Peinhopf, Michael Treu, Andreas Schloegl, Mario Feldvoss
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Publication number: 20120305993Abstract: A semiconductor device includes a gate terminal, at least one control terminal and first and second load terminals and at least one device cell. The at least one device cell includes a MOSFET device having a load path and a control terminal, the control terminal coupled to the gate terminal and a JFET device having a load path and a control terminal, the load path connected in series with the load path of the MOSFET device between the load terminals. The at least one device cell further includes a first coupling transistor having a load path and a control terminal, the load path coupled between the control terminal of the JFET device and one of the source terminal and the gate terminal, and the control terminal coupled to the at least one control terminal of the transistor device.Type: ApplicationFiled: May 31, 2012Publication date: December 6, 2012Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Armin Willmeroth, Franz Hirler, Hans Weber, Michael Treu