Patents by Inventor Michael Treu
Michael Treu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8253225Abstract: An electronic device and manufacturing thereof. One embodiment provides a semiconductor chip having a control electrode and a first load electrode on a first surface and a second load electrode on a second surface. A first lead is electrically coupled to the control electrode. A second lead is electrically coupled to the first load electrode. A third lead is electrically coupled to the first load electrode, the third lead being separate from the second lead. A fourth lead is electrically coupled to the second load electrode, the second and third leads being arranged between the first and fourth leads.Type: GrantFiled: February 22, 2008Date of Patent: August 28, 2012Assignee: Infineon Technologies AGInventors: Ralf Otremba, Marco Seibt, Uwe Kirchner, Wolfgang Peinhopf, Michael Treu, Andreas Schloegl, Mario Feldvoss
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Patent number: 8188482Abstract: One aspect includes a semiconductor device with self-aligned contacts, integrated circuit and manufacturing method. One embodiment provides gate control structures. Each of the gate control structures is configured to control the conductivity of a channel region within a silicon carbide substrate by field effect. A contact hole is self-aligned to opposing sidewalls of adjacent gate control structures by intermediate spacers.Type: GrantFiled: December 22, 2008Date of Patent: May 29, 2012Assignee: Infineon Technologies Austria AGInventors: Michael Treu, Kathrin Rueschenschmidt, Oliver Haeberlen, Franz Auerbach
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Patent number: 8183660Abstract: A semiconductor component is proposed which has a semiconductor body having a first semiconductor zone of the first conduction type, at least one first rectifying junction with respect to the first semiconductor zone, at least one second rectifying junction with respect to the first semiconductor zone, wherein the three rectifying junctions each have a barrier height of different magnitude.Type: GrantFiled: February 26, 2008Date of Patent: May 22, 2012Assignee: Infineon Technologies AGInventors: Michael Rueb, Roland Rupp, Michael Treu
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Publication number: 20120037920Abstract: A semiconductor device as described herein includes a silicon carbide semiconductor body. A trench extends into the silicon carbide semiconductor body at a first surface. A gate dielectric and a gate electrode are formed within the trench. A body zone of a first conductivity type adjoins to a sidewall of the trench, the body zone being electrically coupled to a contact via a body contact zone including a higher maximum concentration of dopants than the body zone. An extension zone of the first conductivity type is electrically coupled to the contact via the body zone, wherein a maximum concentration of dopants of the extension zone along a vertical direction perpendicular to the first surface is higher than the maximum concentration of dopants of the body zone along the vertical direction. A distance between the first surface and a bottom side of the extension zone is larger than the distance between the first surface and the bottom side of the trench.Type: ApplicationFiled: August 12, 2010Publication date: February 16, 2012Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Michael Treu, Ralf Siemieniec
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Patent number: 8102012Abstract: A transistor component having a shielding structure. One embodiment provides a source terminal, a drain terminal and control terminal. A source zone of a first conductivity type is connected to the source terminal. A drain zone of the first conductivity type is connected to the drain terminal. A drift zone is arranged between the source zone and the drain zone. A junction control structure is provided for controlling a junction zone in the drift zone between the drain zone and the source zone, at least including one control zone. A shielding structure is arranged in the drift zone between the junction control structure and the drain zone and at least includes a shielding zone of a second conductivity type being complementarily to the first conductivity type. The shielding zone is connected to a terminal for a shielding potential.Type: GrantFiled: April 17, 2009Date of Patent: January 24, 2012Assignee: Infineon Technologies Austria AGInventors: Dethard Peters, Peter Friedrichs, Rudolf Elpelt, Larissa Wehrhahn-Kilian, Michael Treu, Roland Rupp
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Publication number: 20110227095Abstract: A semiconductor device is disclosed. One embodiment includes a first semiconductor die having a normally-off transistor. In a second semiconductor die a plurality of transistor cells of a normally-on transistor are formed, wherein one of a source terminal/drain terminal of the normally-on transistor is electrically coupled to a gate terminal of the normally-on transistor and the other one the source terminal/drain terminal of the normally-off transistor is electrically coupled to one of a source terminal/drain terminal of the normally-on transistor. The second semiconductor die includes a gate resistor electrically coupled between the gate terminal of the normally-off transistor and respective gates of the plurality of transistor cells. A voltage clamping element is electrically coupled between the gate terminal and the one of the source terminal/drain terminal of the normally-on transistor.Type: ApplicationFiled: March 19, 2010Publication date: September 22, 2011Applicant: Infineon Technologies Austria AGInventors: Michael Treu, Ralf Siemieniec
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Publication number: 20110089481Abstract: A MOS transistor having an increased gate-drain capacitance is described. One embodiment provides a drift zone of a first conduction type. At least one transistor cell has a body zone, a source zone separated from the drift zone by the body zone, and a gate electrode, which is arranged adjacent to the body zone and which is dielectrically insulated from the body zone by a gate dielectric. At least one compensation zone of the first conduction type is arranged in the drift zone. At least one feedback electrode is arranged at a distance from the body zone, which is dielectrically insulated from the drift zone by a feedback dielectric and which is electrically conductively connected to the gate electrode.Type: ApplicationFiled: December 22, 2010Publication date: April 21, 2011Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Armin Willmeroth, Michael Treu
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Patent number: 7910983Abstract: A MOS transistor having an increased gate-drain capacitance is described. One embodiment provides a drift zone of a first conduction type. At least one transistor cell has a body zone, a source zone separated from the drift zone by the body zone, and a gate electrode, which is arranged adjacent to the body zone and which is dielectrically insulated from the body zone by a gate dielectric. At least one compensation zone of the first conduction type is arranged in the drift zone. At least one feedback electrode is arranged at a distance from the body zone, which is dielectrically insulated from the drift zone by a feedback dielectric and which is electrically conductively connected to the gate electrode.Type: GrantFiled: September 30, 2008Date of Patent: March 22, 2011Assignee: Infineon Technologies Austria AGInventors: Armin Willmeroth, Michael Treu
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Publication number: 20100264467Abstract: A transistor component having a shielding structure. One embodiment provides a source terminal, a drain terminal and control terminal. A source zone of a first conductivity type is connected to the source terminal. A drain zone of the first conductivity type is connected to the drain terminal. A drift zone is arranged between the source zone and the drain zone. A junction control structure is provided for controlling a junction zone in the drift zone between the drain zone and the source zone, at least including one control zone. A shielding structure is arranged in the drift zone between the junction control structure and the drain zone and at least includes a shielding zone of a second conductivity type being complementarily to the first conductivity type. The shielding zone is connected to a terminal for a shielding potential.Type: ApplicationFiled: April 17, 2009Publication date: October 21, 2010Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Dethard Peters, Peter Friedrichs, Rudolf Elpelt, Larissa Wehrhahn-Kilian, Michael Treu, Roland Rupp
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Patent number: 7772621Abstract: A semiconductor device with structured current spread region and method is disclosed. One embodiment provides a drift portion of a first conductivity type, a current spread portion of the first conductivity type and first portions of the first conductivity type. The current spread portion and the first portions are arranged in a first plane on the drift portion, wherein the current spread portion surrounds at least partially the first portions. The semiconductor body further includes spaced apart body regions of a second conductivity type which are arranged on the current spread portion. Further, the doping concentration of the current spread portion is higher than the doping concentrations of the drift portion and of the first portions.Type: GrantFiled: September 20, 2007Date of Patent: August 10, 2010Assignee: Infineon Technologies Austria AGInventors: Michael Treu, Roland Rupp, Rudolf Elpelt
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Patent number: 7763506Abstract: A method for making an integrated circuit including vertical junction field effect transistors is disclosed. One embodiment creates a vertical junction field effect transistor using a fault-tolerant or alignment-tolerant production process. The device performance is not harmed, even if misalignments in consecutive semiconductor processing steps occur.Type: GrantFiled: September 10, 2007Date of Patent: July 27, 2010Assignee: Infineon Technologies Austria AGInventors: Michael Treu, Roland Rupp, Heinz Mitlehner, Rudolf Elpelt, Peter Friedrichs, Larissa Wehrhahn-Kilian
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Patent number: 7745273Abstract: A method for manufacturing a semiconductor device. The method includes providing a semiconductor body of a conductivity type, wherein the semiconductor body comprises a first surface. At least one buried region of a second conductivity type is formed in the semiconductor body and at least a surface region of the second conductivity type is formed at the first surface of the semiconductor body, wherein the buried region and the surface region are formed such that they are spaced apart from each other. The buried region is formed by deep implantation of a first dopant of the second conductivity type.Type: GrantFiled: July 30, 2007Date of Patent: June 29, 2010Assignee: Infineon Technologies Austria AGInventors: Michael Treu, Roland Rupp, Michael Rueb, Rudolf Elpelt
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Publication number: 20100155743Abstract: One aspect includes a semiconductor device with self-aligned contacts, integrated circuit and manufacturing method. One embodiment provides gate control structures. Each of the gate control structures is configured to control the conductivity of a channel region within a silicon carbide substrate by field effect. A contact hole is self-aligned to opposing sidewalls of adjacent gate control structures by intermediate spacers.Type: ApplicationFiled: December 22, 2008Publication date: June 24, 2010Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Michael Treu, Kathrin Rueschenschmidt, Oliver Haeberlen, Franz Auerbach
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Publication number: 20100078708Abstract: A MOS transistor having an increased gate-drain capacitance is described. One embodiment provides a drift zone of a first conduction type. At least one transistor cell has a body zone, a source zone separated from the drift zone by the body zone, and a gate electrode, which is arranged adjacent to the body zone and which s dieletrically insulated from the body zone by a gate dielectric. At least one compensation zone of the first conduction type is arranged in the drift zone. At least one feedback electrode is arranged at a distance from the body zone, which is dielectrically insulated from the drift zone by a feedback dielectric and which is electrically conductively connected to the gate electrode.Type: ApplicationFiled: September 30, 2008Publication date: April 1, 2010Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Armin Willmeroth, Michael Treu
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Publication number: 20090212284Abstract: An electronic device and manufacturing thereof. One embodiment provides a semiconductor chip having a control electrode and a first load electrode on a first surface and a second load electrode on a second surface. A first lead is electrically coupled to the control electrode. A second lead is electrically coupled to the first load electrode. A third lead is electrically coupled to the first load electrode, the third lead being separate from the second lead. A fourth lead is electrically coupled to the second load electrode, the second and third leads being arranged between the first and fourth leads.Type: ApplicationFiled: February 22, 2008Publication date: August 27, 2009Applicant: INFINEON TECHNOLOGIES AGInventors: Ralf Otremba, Marco Seibt, Uwe Kirchner, Wolfgang Peinhopf, Michael Treu, Andreas Schloegl, Mario Feldvoss
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Publication number: 20090184373Abstract: A semiconductor device is provided which has a semiconductor substrate. An active cell area having at least one active cell is formed in the semiconductor substrate, wherein at least sections of the active cell area are surrounded by an edge termination region. An integrated gate runner structure is arranged at least partially in the edge termination region and has at least one low electrical resistance portion and at least one high electrical resistance portion which are electrically connected in series with each other.Type: ApplicationFiled: January 18, 2008Publication date: July 23, 2009Applicant: Infineon Technologies Austria AGInventors: Winfried Kaindl, Michael Treu, Holger Kapels, Carolin Tolksdorf, Armin Willmeroth
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Patent number: 7538362Abstract: The invention relates to a lateral semiconductor diode, in which contact metal fillings (6, 7), which run in trenches (3, 4) in particular in a silicon carbide body (1, 2), are interdigitated at a distance from one another, and a rectifying Schottky or pn junction (18) is provided.Type: GrantFiled: August 29, 2005Date of Patent: May 26, 2009Assignee: Infineon Technologies AGInventors: Gabriel Konrad Dehlinger, Michael Treu
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Publication number: 20090085064Abstract: A semiconductor device includes a first semiconductor substrate of a first band-gap material and a second semiconductor substrate of a second band-gap material. The second band-gap material has a lower band-gap than the first band-gap material. A heterojunction is formed between the first semiconductor substrate and the second semiconductor substrate substantially in a first plane. The semiconductor device further includes, in a cross-section which is perpendicular to the first plane, a first semiconductor region of a first conductivity type and a second semiconductor region of the first conductivity type both of which extend from the second semiconductor substrate at least partially into the first semiconductor substrate.Type: ApplicationFiled: September 27, 2007Publication date: April 2, 2009Applicant: Infineon Technologies Austria AGInventors: Michael Rueb, Michael Treu, Armin Willmeroth, Franz Hirler
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Publication number: 20090078971Abstract: A semiconductor device with structured current spread region and method is disclosed. One embodiment provides a drift portion of a first conductivity type, a current spread portion of the first conductivity type and first portions of the first conductivity type. The current spread portion and the first portions are arranged in a first plane on the drift portion, wherein the current spread portion surrounds at least partially the first portions. The semiconductor body further includes spaced apart body regions of a second conductivity type which are arranged on the current spread portion. Further, the doping concentration of the current spread portion is higher than the doping concentrations of the drift portion and of the first portions.Type: ApplicationFiled: September 20, 2007Publication date: March 26, 2009Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Michael Treu, Roland Rupp, Rudolf Elpelt
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Publication number: 20090068803Abstract: A method for making an integrated circuit including vertical junction field effect transistors is disclosed. One embodiment creates a vertical junction field effect transistor using a fault-tolerant or alignment-tolerant production process. The device performance is not harmed, even if misalignments in consecutive semiconductor processing steps occur.Type: ApplicationFiled: September 10, 2007Publication date: March 12, 2009Applicant: Infineon Technologies Austria AGInventors: Michael Treu, Roland Rupp, Heinz Mitlehner, Rudolf Elpelt, Peter Friedrichs, Larissa Wehrhahn-Kilian