Patents by Inventor Mikhail I. Grinchuk
Mikhail I. Grinchuk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11418632Abstract: In one embodiment, a system comprises logic to receive a data packet. The logic is further to identify, based on the data packet, a plurality of candidate rules. The candidate rules may comprise a first candidate rule from a first database of rules and a second candidate rule from a second database of rules. The logic is further to select a rule from among the plurality of candidate rules based on a priority associated with the rule and a determination that the rule matches the data packet. The rule specifies at least one action to be performed on the data packet.Type: GrantFiled: December 15, 2015Date of Patent: August 16, 2022Assignee: Intel CorporationInventors: Anatoli A. Bolotov, Mikhail I. Grinchuk
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Publication number: 20170171362Abstract: In one embodiment, a system comprises logic to receive a data packet. The logic is further to identify, based on the data packet, a plurality of candidate rules. The candidate rules may comprise a first candidate rule from a first database of rules and a second candidate rule from a second database of rules. The logic is further to select a rule from among the plurality of candidate rules based on a priority associated with the rule and a determination that the rule matches the data packet. The rule specifies at least one action to be performed on the data packet.Type: ApplicationFiled: December 15, 2015Publication date: June 15, 2017Applicant: Intel CorporationInventors: Anatoli A. Bolotov, Mikhail I. Grinchuk
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Patent number: 9553612Abstract: An apparatus having a memory and a controller is disclosed. The memory is configured to store a codeword. The controller is configured to (i) determine one or more least-reliable bit positions in a soft-decision version of the codeword in response to failing to decode a hard-decision version of the codeword, (ii) generate a trial codeword by selecting at random a respective value in one or more trial positions among the least-reliable bit positions in the hard-decision codeword and (iii) perform a hard-decision decoding of the trial codeword.Type: GrantFiled: January 28, 2015Date of Patent: January 24, 2017Assignee: Seagate Technology LLCInventors: Anatoli A. Bolotov, Earl T. Cohen, Elyar Gasanov, Mikhail I. Grinchuk, Pavel A. Panteleev
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Patent number: 9497160Abstract: Systems, apparatuses and methods are described for facilitating connection between two or more clients across a network that includes network address translators (NATs). In a particular implementation, the techniques include peer-to-peer (P2P) traffic processing and network address translator (NAT) traversal. Low cost data traffic processing techniques with minimal server intervention are disclosed. The techniques can establish direct connections between clients located in private networks behind NATs. In the case where the clients are each behind a symmetric NAT, the connection can be established indirectly via a non-symmetric NAT (used as a relay) which establishes connection with both symmetric NATs using the disclosed direct connection techniques.Type: GrantFiled: June 24, 2013Date of Patent: November 15, 2016Assignee: Bit Action, Inc.Inventors: Whitfield Diffie, Anatoli Bolotov, Mikhail I. Grinchuk, Ivan Danov, Anton Sabev
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Patent number: 9417847Abstract: A method for generating a design of a multiplier is disclosed. The method generally includes steps (A) to (C). Step (A) may generate a first circuit comprising a plurality of polynomial results of a particular multiplier scheme based on a plurality of parameters of the multiplier. The first circuit is generally configured to multiply a plurality of polynomials. Step (B) may generate a second circuit comprising a plurality of polynomial evaluators based on the parameters. The second circuit may be (i) connected to the first circuit and (ii) configured to evaluate a polynomial modulo operation. Step (C) may generate the design of the multiplier in combinational logic by optimizing a depth of a plurality of logic gates through the first circuit and the second circuit. A product of the polynomials generally resides in a finite field.Type: GrantFiled: September 13, 2011Date of Patent: August 16, 2016Assignee: Intel CorporationInventors: Sergey B. Gashkov, Anatoli A. Bolotov, Mikhail I. Grinchuk, Lav D. Ivanovic, Anatoly A. Chasovshikh, Alexei V. Galatenko, Igor V. Kucherenko
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Publication number: 20150333776Abstract: An apparatus having a memory and a controller is disclosed. The memory is configured to store a codeword. The controller is configured to (i) determine one or more least-reliable bit positions in a soft-decision version of the codeword in response to failing to decode a hard-decision version of the codeword, (ii) generate a trial codeword by selecting at random a respective value in one or more trial positions among the least-reliable bit positions in the hard-decision codeword and (iii) perform a hard-decision decoding of the trial codeword.Type: ApplicationFiled: January 28, 2015Publication date: November 19, 2015Inventors: Anatoli A. Bolotov, Earl T. Cohen, Elyar Gasanov, Mikhail I. Grinchuk, Pavel A. Panteleev
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Patent number: 8996969Abstract: A data processing system includes a decoder circuit, syndrome calculation circuit and hash calculation circuit. The decoder circuit is operable to apply a decoding algorithm to a decoder input based on a first portion of a composite matrix to yield a codeword. The syndrome calculation circuit is operable to calculate a syndrome based on the codeword and on the first portion of the composite matrix. The hash calculation circuit is operable to calculate a hash based on a second portion of the composite matrix. The decoder circuit is also operable to correct the codeword on the hash when the syndrome indicates that the codeword based on the first portion of the composite matrix is correct but a second test indicates that the codeword is miscorrected.Type: GrantFiled: December 8, 2012Date of Patent: March 31, 2015Assignee: LSI CorporationInventors: Anatoli A. Bolotov, Shaohua Yang, Zongwang Li, Mikhail I Grinchuk, Lav D. Ivanovic, Fan Zhang, Yang Han
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Patent number: 8929009Abstract: A data processing system is disclosed including a data decoder circuit, an error handling circuit and a syndrome checker circuit. The data decoder circuit is operable to apply a data decode algorithm to a decoder input to yield a decoded output, and to calculate a syndrome indicating an error level for the decoded output. The error handling circuit is operable to determine whether any errors in the decoded output involve user data bits. The syndrome checker circuit is operable to trigger the error handling circuit based at least in part on the syndrome.Type: GrantFiled: February 26, 2013Date of Patent: January 6, 2015Assignee: LSI CorporationInventors: Shaohua Yang, Anatoli A. Bolotov, Chung-Li Wang, Zongwang Li, Shu Li, Mikhail I Grinchuk
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Patent number: 8898539Abstract: A receive path of a communications system comprises an error-correction decoder, an error-detection decoder, and a codeword adjuster. The error-correction decoder performs error-correction decoding on a received codeword to generate a valid codeword. The error-detection decoder performs error-detection decoding on the valid codeword to determine whether or not the valid codeword is the correct codeword that was transmitted. If the valid codeword is not the correct codeword, then the codeword adjuster generates an adjusted valid codeword by applying an error vector to the valid codeword. The error-detection decoder performs error-detection decoding on the adjusted valid codeword to determine whether or not the adjusted valid codeword is the correct codeword. When the error-correction decoder generates an incorrect valid codeword, adjusting the valid codeword enables the receive path to recover the correct codeword without retransmitting or re-detecting the codeword.Type: GrantFiled: September 12, 2012Date of Patent: November 25, 2014Assignee: LSI CorporationInventors: Yang Han, Shaohua Yang, Zongwang Li, Fan Zhang, Anatoli A. Bolotov, Mikhail I. Grinchuk, Paul G. Filseth, Lav D. Ivanovic
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Publication number: 20140325303Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for encoding data sets.Type: ApplicationFiled: May 2, 2013Publication date: October 30, 2014Applicant: LSI CorporationInventors: Shaohua Yang, Anatoli A. Bolotov, Mikhail I. Grinchuk
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Publication number: 20140281284Abstract: A method includes receiving a multi-port read request for retrieval of data stored in three memories, each comprising two memory modules and a parity module. The multi-port read request is associated with first data stored at a first memory address, second data stored at a second memory address, and third data stored at a third memory address. When the first memory address, the second memory address, and the third memory address are associated with a first memory module, first data is retrieved from the first memory module, second data is reconstructed using data from a second memory module and a first parity module, and third data is reconstructed using data from a fourth memory module and a seventh memory module. The first data, the second data, and the third data are provided in response to the multi-port read request.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: Stefan G. Block, Ting Zhou, Mikhail I. Grinchuk, Anatoli A. Bolotov, Lav D. Ivanovic
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Patent number: 8831221Abstract: In described embodiments, a unified Crypto Functional Unit (CFU) block architecture provides a capability for advanced communication processors to provide parallel and concurrent processing of multiple crypto operations/transactions within high-speed hardware to support different security standards (e.g. from IPsec, 3GPP). In particular, each CFU block of the unified CFU block architecture comprises a FIFO-based interface, switch, and wrapped cipher/hasher. The unified CFU block architecture allows for drop-in solutions for cipher blocks in ASIC designs with crypto function blocks.Type: GrantFiled: September 28, 2010Date of Patent: September 9, 2014Assignee: LSI CorporationInventors: Anatoli A. Bolotov, Mikhail I. Grinchuk, Lav Ivanovic, Igor Kucherenko, Alexei Galatenko
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Patent number: 8806227Abstract: A method of storing sensitive data by generating randomization values, transforming the sensitive data and the randomization values into a result, and storing separate portions of the result on at least two storage devices, such that the sensitive data cannot be disclosed if any one of the storage devices is compromised.Type: GrantFiled: January 8, 2007Date of Patent: August 12, 2014Assignee: LSI CorporationInventors: Mikhail I. Grinchuk, Anatoli A. Bolotov, Ranko Scepanovic, Robert D. Waldron
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Patent number: 8797668Abstract: Systems, methods, devices, circuits for data processing, and more particularly to penalty based multi-variant encoding of data.Type: GrantFiled: May 2, 2013Date of Patent: August 5, 2014Assignee: LSI CorporationInventors: Mikhail I Grinchuk, Anatoli A. Bolotov, Shaohua Yang, Victor Krachkovsky, Zongwang Li
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Patent number: 8782487Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, data processing systems are disclosed that include a data decoding circuit having a data decoder circuit, an element modification circuit, an element modification log, and a mis-correction detection circuit.Type: GrantFiled: April 18, 2012Date of Patent: July 15, 2014Assignee: LSI CorporationInventors: Shaohua Yang, Yang Han, Chung-Li Wang, Mikhail I. Grinchuk, Anatoli A. Bolotov, Lav D. Ivanovic
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Publication number: 20140168811Abstract: A data processing system is disclosed including a data decoder circuit, an error handling circuit and a syndrome checker circuit. The data decoder circuit is operable to apply a data decode algorithm to a decoder input to yield a decoded output, and to calculate a syndrome indicating an error level for the decoded output. The error handling circuit is operable to determine whether any errors in the decoded output involve user data bits. The syndrome checker circuit is operable to trigger the error handling circuit based at least in part on the syndrome.Type: ApplicationFiled: February 26, 2013Publication date: June 19, 2014Applicant: LSI CORPORATIONInventors: Shaohua Yang, Anatoli A. Bolotov, Chung-Li Wang, Zongwang Li, Shu Li, Mikhail I. Grinchuk
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Publication number: 20140164866Abstract: A data processing system is disclosed including a decoder circuit, syndrome calculation circuit and hash calculation circuit. The decoder circuit is operable to apply a decoding algorithm to a decoder input based on a first portion of a composite matrix to yield a codeword. The syndrome calculation circuit is operable to calculate a syndrome based on the codeword and on the first portion of the composite matrix. The hash calculation circuit is operable to calculate a hash based on a second portion of the composite matrix. The decoder circuit is also operable to correct the codeword on the hash when the syndrome indicates that the codeword based on the first portion of the composite matrix is correct but a second test indicates that the codeword is miscorrected.Type: ApplicationFiled: December 8, 2012Publication date: June 12, 2014Applicant: LSI CORPORATIONInventors: Anatoli A. Bolotov, Shaohua Yang, Zongwang Li, Mikhail I. Grinchuk, Lav D. Ivanovic, Fan Zhang, Yang Han
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Patent number: 8683291Abstract: Described embodiments provide for a frame check sequence (FCS) module with a cyclic redundancy check (CRC) unit that receives a data block (padded, if necessary, to a maximum width) and a first state vector and computes an internal vector based on an extended CRC transition matrix. The FCS module further includes a set of matrix units, each matrix unit configured to multiply the internal vector by a corresponding correction matrix wherein the multiplications result in a set of products. A multiplexer selects, by a control signal determined by a maximum number of bytes and the original width, a second state vector from the set of products.Type: GrantFiled: June 16, 2011Date of Patent: March 25, 2014Assignee: LSI CorporationInventors: Mikhail I. Grinchuk, Anatoli A. Bolotov, Lav Ivanovic
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Publication number: 20140075264Abstract: A receive path of a communications system comprises an error-correction decoder, an error-detection decoder, and a codeword adjuster. The error-correction decoder performs error-correction decoding on a received codeword to generate a valid codeword. The error-detection decoder performs error-detection decoding on the valid codeword to determine whether or not the valid codeword is the correct codeword that was transmitted. If the valid codeword is not the correct codeword, then the codeword adjuster generates an adjusted valid codeword by applying an error vector to the valid codeword. The error-detection decoder performs error-detection decoding on the adjusted valid codeword to determine whether or not the adjusted valid codeword is the correct codeword. When the error-correction decoder generates an incorrect valid codeword, adjusting the valid codeword enables the receive path to recover the correct codeword without retransmitting or re-detecting the codeword.Type: ApplicationFiled: September 12, 2012Publication date: March 13, 2014Applicant: LSI CorporationInventors: Yang Han, Shaohua Yang, Zongwang Li, Fan Zhang, Anatoli A. Bolotov, Mikhail I. Grinchuk, Paul G. Filseth, Lav D. Ivanovic
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Publication number: 20130283114Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, data processing systems are disclosed that include a data decoding circuit having a data decoder circuit, an element modification circuit, an element modification log, and a mis-correction detection circuit.Type: ApplicationFiled: April 18, 2012Publication date: October 24, 2013Inventors: Shaohua Yang, Yang Han, Chung-Li Wang, Mikhail I. Grinchuk, Anatoli A. Bolotov, Lav D. Ivanovic