Patents by Inventor Mikhail I. Grinchuk
Mikhail I. Grinchuk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7218138Abstract: A circuit and a method for operating the circuit are disclosed. A first step of the method generally comprises generating a plurality of first intermediate signals in two parallel first operations each responsive to a respective half of a plurality of input signals. A second step involves generating a plurality of result signals in a plurality of first logical operations each responsive to at most two of the first intermediate signals. A third step includes generating a first output signal as a particular one of the result signals, wherein a first delay from the first intermediate signals to the first output signal is at most through one logical gate. A fourth step of the method generally comprises generating a second output signal for a second threshold function in a logical OR operation of the result signals except for the particular one result signal.Type: GrantFiled: December 23, 2004Date of Patent: May 15, 2007Assignee: LSI CorporationInventor: Mikhail I. Grinchuk
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Patent number: 7213043Abstract: A fixed-point arithmetic unit comprises a plurality of full-adders and half-adders arranged in at least an input row and an output row. A plurality of inputs to the input row is arranged to receive bits comprising a sparse-redundant representation of the integer. A converter converts 1-redundant representations of the integer to the space (1/K)-redundant representations. A process is described to design rows of a multiplier by identifying a distribution of multiplication product groups, and transforming the distribution of multiplication product groups to adders to occupy a highest unoccupied row of the multiplier.Type: GrantFiled: January 21, 2003Date of Patent: May 1, 2007Assignee: LSI Logic CorporationInventor: Mikhail I. Grinchuk
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Patent number: 7210083Abstract: The present invention provides a system and method for implementing postponed quasi-masking test output compression in an integrated circuit. The system includes a compressor for compressing a test response from N scan chains of an integrated circuit into M outputs. The test response may indicate faults in the integrated circuit. M and N are positive integers. The system further includes a correctable multiple input signature register with a size of M, which is communicatively coupled to the compressor. The correctable multiple input signature register is suitable for receiving the M outputs from the compressor as data inputs (s[0], . . . , s[M?1]) and receiving M correction bits (c[0], . . . , c[M?1]) and L address bits (a[0], . . . , a[L?1]) as correction inputs, L being a positive integer, 2L>=M. The correctable multiple input signature register is suitable for detecting faults when there is no or at least one unknown value (i.e., X-value) in the test response.Type: GrantFiled: December 16, 2004Date of Patent: April 24, 2007Assignee: LSI Logic CorporationInventors: Mikhail I. Grinchuk, Ahmad Alvamani, Erik Chmelar
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Patent number: 7206983Abstract: The present invention provides a segmented addressable scan architecture and method for implementing scan-based testing of integrated circuits. A scan chain is divided into a plurality of segments. For a test pattern, compatible segments of the plurality of segments are grouped into compatibility classes. All compatible segments or a subset of them within one of the compatibility classes are simultaneously loaded through selective activation.Type: GrantFiled: March 31, 2005Date of Patent: April 17, 2007Assignee: LSI Logic CorporationInventors: Ahmad A. Alyamani, Mikhail I. Grinchuk, Erik Chmelar
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Patent number: 7185039Abstract: A method of modular exponentiation includes receiving as input a first number, a second number, and a modulus for calculating a residue of a product of the first number times the second number modulo the modulus; partitioning the first number into a selected number of pieces; calculating a first product of one of the pieces times the second number; adding a previous intermediate result to the first product to generate a first sum; shifting the first sum by a selected number of bit positions to generate a second product; and reducing a bit width of the second product to generate an intermediate result wherein the intermediate result has a bit width that is less than a bit width of the second product and has a residue that is identical to a residue of the second product modulo the modulus.Type: GrantFiled: May 19, 2003Date of Patent: February 27, 2007Assignee: LSI Logic CorporationInventor: Mikhail I. Grinchuk
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Patent number: 7020865Abstract: Logic circuits for logical operations, based on a function fN=x1 OR (x2 AND (x3 OR (x4 AND . . . xN . . . ))) or f?N=x1 AND (x2 OR (x3 AND (x4 OR . . . xN . . . ))), are designed by defining a top portion of the logic circuit based on a pre-selected pattern of 2-input $ and @ gates. The top portion has N inputs and approximately N/3 outputs. A smaller logic circuit is defined having approximately N/3 inputs coupled to the outputs of the top portion. In one embodiment, the circuit is designed for a circuit having N? inputs, where N? is 3n or 2*3n, and the N??N most significant inputs are set to fixed values. The extra gates are removed resulting in a minimum depth circuit. In another embodiment, the depth is further reduced in some cases by designing a circuit for N?1 inputs and transforming the circuit to an N-input circuit. The $ and @ gates are converted to AND and/or OR gates, depending on the function.Type: GrantFiled: June 24, 2003Date of Patent: March 28, 2006Assignee: LSI Logic CorporationInventors: Mikhail I. Grinchuk, Anatoli A. Bolotov
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Patent number: 7020589Abstract: An optimization apparatus and method optimizes a functional block within a netlist of an integrated circuit design. A corresponding delay value is assigned to each of a plurality of pins of the block. Each pin corresponds to a respective signal path through the block. The delay values together form a delay value combination, which is selected from a continuous set of possible combinations in which each combination in the set satisfies a predetermined criteria. A circuit configuration for the block is then generated with a plurality of logic cells that are interconnected in the netlist such that the respective signal paths have delays through the block that are based on the corresponding delay values.Type: GrantFiled: September 26, 2001Date of Patent: March 28, 2006Assignee: LSI Logic CorporationInventors: Partha P. Datta Ray, Mikhail I. Grinchuk, Pedja Raspopovic
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Patent number: 6928591Abstract: A controller for repairing a redundant memory circuit includes a fault storage matrix for mapping a repair solution, a plurality of registers for storing row and column coordinates of the repair solution, and a repair solution calculator coupled to the plurality of registers and the fault storage matrix for receiving an x-coordinate and a y-coordinate of a defective memory cell in the redundant memory circuit and for determining whether a repair solution may be found from the fault storage matrix.Type: GrantFiled: December 23, 2002Date of Patent: August 9, 2005Assignee: LSI Logic CorporationInventors: Mikhail I. Grinchuk, Ranko Scepanovic, Ghasi R. Agrawal
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Publication number: 20040236813Abstract: A method of modular exponentiation includes receiving as input a first number, a second number, and a modulus for calculating a residue of a product of the first number times the second number modulo the modulus; partitioning the first number into a selected number of pieces; calculating a first product of one of the pieces times the second number; adding a previous intermediate result to the first product to generate a first sum; shifting the first sum by a selected number of bit positions to generate a second product; and reducing a bit width of the second product to generate an intermediate result wherein the intermediate result has a bit width that is less than a bit width of the second product and has a residue that is identical to a residue of the second product modulo the modulus.Type: ApplicationFiled: May 19, 2003Publication date: November 25, 2004Inventor: Mikhail I. Grinchuk
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Publication number: 20040143619Abstract: A fixed-point arithmetic unit comprises a plurality of full-adders and half-adders arranged in at least an input row and an output row. A plurality of inputs to the input row is arranged to receive bits comprising a sparse-redundant representation of the integer. A converter converts 1-redundant representations of the integer to the space (1/K)-redundant representations. A process is described to design rows of a multiplier by identifying a distribution of multiplication product groups, and transforming the distribution of multiplication product groups to adders to occupy a highest unoccupied row of the multiplier.Type: ApplicationFiled: January 21, 2003Publication date: July 22, 2004Inventor: Mikhail I. Grinchuk
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Publication number: 20040128593Abstract: A controller for repairing a redundant memory circuit includes a fault storage matrix for mapping a repair solution, a plurality of registers for storing row and column coordinates of the repair solution, and a repair solution calculator coupled to the plurality of registers and the fault storage matrix for receiving an x-coordinate and a y-coordinate of a defective memory cell in the redundant memory circuit and for determining whether a repair solution may be found from the fault storage matrix.Type: ApplicationFiled: December 23, 2002Publication date: July 1, 2004Applicant: LSI Logic CorporationInventors: Mikhail I. Grinchuk, Ranko Scepanovic, Ghasi R. Agrawal
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Patent number: 6704915Abstract: A process for re-designing IC chips by altering the positions of cells from a first to a second IC chip layout. An x,y grid is established for the first and second IC layouts such that each cell has identifying x,y coordinates in the first layout. Columns are established in the second layout based on the bounds of the second layout in the x-direction. The cells are sorted to the columns in the order of cell x-coordinates to establish new x-coordinates for each cell based on the x-coordinates of the respective column. The cells are sorted in each column to establish y-coordinates for each cell based on the height of the cells in the column and the height of the column.Type: GrantFiled: June 12, 2001Date of Patent: March 9, 2004Assignee: LSI Logic CorporationInventors: Alexander E. Andreev, Ranko Scepanovic, Mikhail I. Grinchuk
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Patent number: 6701499Abstract: The present invention is directed to a system and method for effective approximation of smooth functions. In an aspect of the present invention, a method for approximating a smooth function for implementation in an integrated circuit design includes receiving a function f for computation with an accuracy of m bits by an integrated circuit. The function is computed based on an operator with one more output than the accuracy of m bits and a value of f′ is determined by choosing from one of the at least two numbers computed utilizing the operator with one more output. The value may be chosen based on complexity issues in the construction of a binary decision diagram for use in designing the integrated circuit.Type: GrantFiled: December 3, 2002Date of Patent: March 2, 2004Assignee: LSI Logic CorporationInventor: Mikhail I. Grinchuk
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Publication number: 20030237068Abstract: The present invention is directed to a system and method for effective approximation of smooth functions. In an aspect of the present invention, a method for approximating a smooth function for implementation in an integrated circuit design includes receiving a function f for computation with an accuracy of m bits by an integrated circuit. The function is computed based on an operator with one more output than the accuracy of m bits and a value of f′ is determined by choosing from one of the at least two numbers computed utilizing the operator with one more output. The value may be chosen based on complexity issues in the construction of a binary decision diagram for use in designing the integrated circuit.Type: ApplicationFiled: December 3, 2002Publication date: December 25, 2003Inventor: Mikhail I. Grinchuk
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Patent number: 6643832Abstract: A pre-placement delay model for a logical function block of an integrated circuit design includes a fan-in count variable, a fan-out count variable and a delay variable. The fan-in count variable has a value indicative of a number of inputs to the logical function block. The fan-out count variable has a value indicative of the number of inputs of other logical function blocks that are driven by an output of the logical function block. The delay variable has a value that is a function of the binary logarithm of the fan-in count variable and the binary logarithm of the fan-out count variable.Type: GrantFiled: September 26, 2001Date of Patent: November 4, 2003Assignee: LSI Logic CorporationInventors: Partha P. Data Ray, Mikhail I. Grinchuk, Pedja Raspopovic
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Patent number: 6536027Abstract: A metal wire for a feature of a cell is extended using a grid based on a metal layer of the cell. Each grid element is assigned an “F” designator representing the metal wire being extended, an “E” designator representing blockages to extension of the metal wire, such as metal wires of other features, or a “U” designator representing grid elements that are neither F-designated, nor E-designated grid elements. U-designated grid elements that are neighbors to E-designated grid elements are identified. A minimum length path is defined through the U-designated grid elements that are not neighbors to E-designated grid elements between the cell boundary and a F-designated grid element.Type: GrantFiled: December 13, 2000Date of Patent: March 18, 2003Assignee: LSI Logic CorporationInventors: Mikhail I. Grinchuk, Alexander E. Andreev, Ranko Scepanovic
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Publication number: 20020124233Abstract: A process for re-designing IC chips by altering the positions of cells from a first to a second IC chip layout. An x,y grid is established for the first and second IC layouts such that each cell has identifying x,y coordinates in the first layout. Columns are established in the second layout based on the bounds of the second layout in the x-direction. The cells are sorted to the columns in the order of cell x-coordinates to establish new x-coordinates for each cell based on the x-coordinates of the respective column. The cells are sorted in each column to establish y-coordinates for each cell based on the height of the cells in the column and the height of the column.Type: ApplicationFiled: January 8, 2001Publication date: September 5, 2002Inventors: Alexander E. Andreev, Ranko Scepanovic, Mikhail I. Grinchuk