Patents by Inventor Mikhail I. Grinchuk
Mikhail I. Grinchuk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8499264Abstract: A method of designing a logic circuit based on one of the functions of the form fn=x1 (x2 & (x3 (x4 & . . . xn . . . ))) and f?n=x1 & (x2 (x3 & (x4 . . . xn . . . ))), by (a) selecting n as the number of variables of the logic circuit, (b) testing n against a threshold, (c) for values of n less than the threshold, using a first algorithm to design the logic circuit, (d) for values of n greater than the threshold, using a second algorithm to design the logic circuit.Type: GrantFiled: February 29, 2012Date of Patent: July 30, 2013Assignee: LSI CorporationInventor: Mikhail I. Grinchuk
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Patent number: 8416666Abstract: The present invention is related to systems and methods for characterizing circuit operation, and more particularly to systems and methods for modifying a data decoding process.Type: GrantFiled: April 20, 2012Date of Patent: April 9, 2013Assignee: LSI CorporationInventors: Fan Zhang, Yang Han, Anatoli A. Bololov, Mikhail I. Grinchuk, Shaohua Yang
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Patent number: 8359479Abstract: The present invention is a cryptoengine configured for providing countermeasures against attacks, including: an input/output (I/O) control unit, a memory, a controller, and an Arithmetic Logic Unit (ALU). The memory is communicatively coupled with the I/O control unit, receives inputs from the I/O control unit, and provides outputs to the I/O control unit based upon the received inputs. The controller is communicatively coupled with the I/O control unit for transmitting and receiving control signals. The ALU includes a plurality of storage components and computational components. The ALU is communicatively coupled with the controller and receives commands from/transmits status bits and flags to the controller. The ALU is further communicatively coupled with the memory and is configured for providing output signals to/receiving input signals from the memory. Further, the cryptoengine is configured for being communicatively coupled with a host computing device.Type: GrantFiled: July 17, 2008Date of Patent: January 22, 2013Assignee: LSI CorporationInventors: Mikhail I. Grinchuk, Anatoli A. Bolotov, Lav D. Ivanovic, Paul G. Filseth
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Publication number: 20120324319Abstract: Described embodiments provide for a frame check sequence (FCS) module with a cyclic redundancy check (CRC) unit that receives a data block (padded, if necessary, to a maximum width) and a first state vector and computes an internal vector based on an extended CRC transition matrix. The FCS module further includes a set of matrix units, each matrix unit configured to multiply the internal vector by a corresponding correction matrix wherein the multiplications result in a set of products. A multiplexer selects, by a control signal determined by a maximum number of bytes and the original width, a second state vector from the set of products.Type: ApplicationFiled: June 16, 2011Publication date: December 20, 2012Inventors: Mikhail I. Grinchuk, Anatoli A. Bolotov, Lav Ivanovic
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Patent number: 8302083Abstract: An architecture includes a controller. The controller is configured to receive a microprogram. The microprogram is configured for performing at least one of hierarchical or a sequence of polynomial computations. The architecture also includes an arithmetic logic unit (ALU) communicably coupled to the controller. The ALU is controlled by the controller. Additionally, the microprogram is compiled prior to execution by the controller, the microprogram is compiled into a plurality of binary tables, and the microprogram is programmed in a command language in which each command includes a first portion for indicating at least one of a command or data transferred to the ALU, and a second portion for including a control command to the controller. The architecture and implementation of the programmable controller may be for cryptographic applications, including those related to public key cryptography.Type: GrantFiled: January 23, 2009Date of Patent: October 30, 2012Assignee: LSI CorporationInventors: Anatoli A. Bolotov, Mikhail I. Grinchuk, Lav Ivanovic, Alexei Galatenko
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Publication number: 20120226731Abstract: A method for generating a design of a multiplier is disclosed. The method generally includes steps (A) to (C). Step (A) may generate a first circuit comprising a plurality of polynomial results of a particular multiplier scheme based on a plurality of parameters of the multiplier. The first circuit is generally configured to multiply a plurality of polynomials. Step (B) may generate a second circuit comprising a plurality of polynomial evaluators based on the parameters. The second circuit may be (i) connected to the first circuit and (ii) configured to evaluate a polynomial modulo operation. Step (C) may generate the design of the multiplier in combinational logic by optimizing a depth of a plurality of logic gates through the first circuit and the second circuit. A product of the polynomials generally resides in a finite field.Type: ApplicationFiled: September 13, 2011Publication date: September 6, 2012Inventors: Sergey B. Gashkov, Anatoli A. Bolotov, Mikhail I. Grinchuk, Lav D. Ivanovic, Anatoly A. Chasovshikh, Alexei V. Galatenko, Igor V. Kucherenko
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Publication number: 20120159407Abstract: A method of designing a logic circuit based on one of the functions of the form fn=x1 (x2 & (x3 (x4 & . . . xn . . . ))) and f?n=x1 & (x2 (x3 & (x4 . . . xn . . . ))), by (a) selecting n as the number of variables of the logic circuit, (b) testing n against a threshold, (c) for values of n less than the threshold, using a first algorithm to design the logic circuit, (d) for values of n greater than the threshold, using a second algorithm to design the logic circuit.Type: ApplicationFiled: February 29, 2012Publication date: June 21, 2012Applicant: LSI CORPORATIONInventor: Mikhail I. Grinchuk
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Patent number: 8166441Abstract: A method of designing a logic circuit based on one of the functions of the form fn=x1 (x2 & (x3 (x4 & . . . xn . . . ))) and f?n=x1 & (x2 (x3 & (x4 . . . xn . . . ))), by (a) selecting n as the number of variables of the logic circuit, (b) testing n against a threshold, (c) for values of n less than the threshold, using a first algorithm to design the logic circuit, (d) for values of n greater than the threshold, using a second algorithm to design the logic circuit.Type: GrantFiled: October 9, 2008Date of Patent: April 24, 2012Assignee: LSI CorporationInventor: Mikhail I. Grinchuk
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Publication number: 20120076298Abstract: In described embodiments, a unified Crypto Functional Unit (CFU) block architecture provides a capability for advanced communication processors to provide parallel and concurrent processing of multiple crypto operations/transactions within high-speed hardware to support different security standards (e.g. from IPsec, 3GPP). In particular, each CFU block of the unified CFU block architecture comprises a FIFO-based interface, switch, and wrapped cipher/hasher. The unified CFU block architecture allows for drop-in solutions for cipher blocks in ASIC designs with crypto function blocks.Type: ApplicationFiled: September 28, 2010Publication date: March 29, 2012Inventors: Anatoli A. Bolotov, Mikhail I. Grinchuk, Lav Ivanovic, Igor Kucherenko, Alexei Galatenko
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Publication number: 20110255689Abstract: In one embodiment, a multi-mode Advanced Encryption Standard (MM-AES) module for a storage controller is adapted to perform interleaved processing of multiple data streams, i.e., concurrently encrypt and/or decrypt string-data blocks from multiple data streams using, for each data stream, a corresponding cipher mode that is any one of a plurality of AES cipher modes. The MM-AES module receives a string-data block with (a) a corresponding key identifier that identifies the corresponding module-cached key and (b) a corresponding control command that indicates to the MM-AES module what AES-mode-related processing steps to perform on the data block. The MM-AES module generates, updates, and caches masks to preserve inter-block information and allow the interleaved processing. The MM-AES module uses an unrolled and pipelined architecture where each processed data block moves through its processing pipeline in step with correspondingly moving key, auxiliary data, and instructions in parallel pipelines.Type: ApplicationFiled: April 15, 2010Publication date: October 20, 2011Applicant: LSI CORPORATIONInventors: Anatoli Bolotov, Mikhail I. Grinchuk, Timothy E. Hoglund, Lav D. Ivanovic, Paul G. Filseth
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Patent number: 8023644Abstract: An architecture for a block cipher, where the architecture includes functional units that are logically reconfigurable so as to be able to both encrypt clear text into cipher text and decrypt cipher text into clear text using more than one block cipher mode based on at least one of advanced encryption standard and data encryption standard.Type: GrantFiled: October 30, 2007Date of Patent: September 20, 2011Assignee: LSI CorporationInventors: Anatoli A. Bolotov, Mikhail I. Grinchuk, Lav D. Ivanovic, Paul G. Filseth, Anton I. Sabev
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Patent number: 7890565Abstract: A combination of an infrequently-called tiny multiplication unit and a “differential” unit that quickly computes T(n+1) basing on known Tn. The schedule (how often the multiplication unit is called) can be considered as a parameter of the algorithm. The proposed architecture of the “differential” unit is efficient both in terms of speed (delay) and area (gate count).Type: GrantFiled: April 30, 2007Date of Patent: February 15, 2011Assignee: LSI CorporationInventors: Anatoli Bolotov, Mikhail I. Grinchuk
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Publication number: 20100191935Abstract: An architecture includes a controller. The controller is configured to receive a microprogram. The microprogram is configured for performing at least one of hierarchical or a sequence of polynomial computations. The architecture also includes an arithmetic logic unit (ALU) communicably coupled to the controller. The ALU is controlled by the controller. Additionally, the microprogram is compiled prior to execution by the controller, the microprogram is compiled into a plurality of binary tables, and the microprogram is programmed in a command language in which each command includes a first portion for indicating at least one of a command or data transferred to the ALU, and a second portion for including a control command to the controller. The architecture and implementation of the programmable controller may be for cryptographic applications, including those related to public key cryptography.Type: ApplicationFiled: January 23, 2009Publication date: July 29, 2010Inventors: Anatoli A. Bolotov, Mikhail I. Grinchuk, Lav Ivanovic, Alexei Galatenko
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Publication number: 20100017622Abstract: The present invention is a cryptoengine configured for providing countermeasures against attacks, including: an input/output (I/O) control unit, a memory, a controller, and an Arithmetic Logic Unit (ALU). The memory is communicatively coupled with the I/O control unit, receives inputs from the I/O control unit, and provides outputs to the I/O control unit based upon the received inputs. The controller is communicatively coupled with the I/O control unit for transmitting and receiving control signals. The ALU includes a plurality of storage components and computational components. The ALU is communicatively coupled with the controller and receives commands from/transmits status bits and flags to the controller. The ALU is further communicatively coupled with the memory and is configured for providing output signals to/receiving input signals from the memory. Further, the cryptoengine is configured for being communicatively coupled with a host computing device.Type: ApplicationFiled: July 17, 2008Publication date: January 21, 2010Inventors: Mikhail I. Grinchuk, Anatoli A. Bolotov, Lav D. Ivanovic, Paul G. Filseth
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Publication number: 20090100390Abstract: A method of designing a logic circuit based on one of the functions of the form fn=x1 (x2 & (x3 (x4 & . . . xn . . . ))) and f?n=x1 & (x2 (x3 & (x4 . . . xn . . . ))), by (a) selecting n as the number of variables of the logic circuit, (b) testing n against a threshold, (c) for values of n less than the threshold, using a first algorithm to design the logic circuit, (d) for values of n greater than the threshold, using a second algorithm to design the logic circuit.Type: ApplicationFiled: October 9, 2008Publication date: April 16, 2009Applicant: LSI CORPORATIONInventor: Mikhail I. Grinchuk
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Patent number: 7461107Abstract: A fixed-point arithmetic unit comprises a plurality of full-adders and half-adders arranged in at least an input row and an output row. A plurality of inputs to the input row is arranged to receive bits comprising a sparse-redundant representation of the integer. A converter converts 1-redundant representations of the integer to the space (1/K)-redundant representations. A process is described to design rows of a multiplier by identifying a distribution of multiplication product groups, and transforming the distribution of multiplication product groups to adders to occupy a highest unoccupied row of the multiplier.Type: GrantFiled: March 22, 2007Date of Patent: December 2, 2008Assignee: LSI CorporationInventor: Mikhail I. Grinchuk
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Publication number: 20080270505Abstract: A combination of an infrequently-called tiny multiplication unit and a “differential” unit that quickly computes T (n+1) basing on known T n. The schedule (how often the multiplication unit is called) can be considered as a parameter of the algorithm. The proposed architecture of the “differential” unit is efficient both in terms of speed (delay) and area (gate count).Type: ApplicationFiled: April 30, 2007Publication date: October 30, 2008Applicant: LSI LOGIC CORPORATIONInventors: Anatoli Bolotov, Mikhail I. Grinchuk
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Publication number: 20080130873Abstract: A circuit for implementing elliptic curve and hyperelliptic curve encryption and decryption operations, having a read only memory with no more than about two kilobytes of accessible memory, containing first programming instructions. An arithmetic logic unit has access to second programming instructions that are resident in a gate-level program disposed in the arithmetic logic unit, and is operable to receive data from no more than one input FIFO register. A microcontroller has no more than about two thousand gates, and is adapted to read the first programming instructions from the read only memory, send control signals to the arithmetic logic unit, and receive flags from the arithmetic logic unit. The arithmetic unit reads the third programming instructions, selectively performs elliptic curve and hyperelliptic curve encryption and decryption operations on the data according to the second programming instructions and the microcontroller, and sends output to no more than one output FIFO register.Type: ApplicationFiled: December 4, 2007Publication date: June 5, 2008Applicant: LSI CorporationInventors: Anatoli A. Bolotov, Mikhail I. Grinchuk, Paul G. Filseth, Lav D. Ivanovic
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Publication number: 20080130872Abstract: An architecture for a block cipher, where the architecture includes functional units that are logically reconfigurable so as to be able to both encrypt clear text into cipher text and decrypt cipher text into clear text using more than one block cipher mode based on at least one of advanced encryption standard and data encryption standard.Type: ApplicationFiled: October 30, 2007Publication date: June 5, 2008Applicant: LSI CorporationInventors: Anatoli A. Bolotov, Mikhail I. Grinchuk, Lav D. Ivanovic, Paul G. Filseth, Anton I. Sabev
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Patent number: 7328386Abstract: The invention relates to a method for using checksums in X-tolerant test response compaction in scan-based testing of integrated circuits. Flip-flops of a chip are treated as points of a discrete geometrical structure described in terms of points and lines, with each point representing a MUXed flip-flop holding a value, each line representing a checksum, and each set of parallel lines representing scan chains. The checksums for the flip-flops are calculated along a direction.Type: GrantFiled: May 18, 2005Date of Patent: February 5, 2008Assignee: LSI Logic CorporationInventors: Mikhail I. Grinchuk, Ahmad A. Alyamani, Erik Chmelar