Abstract: A method for intraoperative planning and facilitating a revision arthroplasty procedure includes displaying a virtual model of a bone, capturing positions of a tracked probe as the tracked probe contacts points at a perimeter of a primary implant component coupled to the bone, generating a virtual representation of an interface between the primary implant component and the virtual model of the bone using the positions of the tracked probe, planning a bone resection using the virtual representation of the interface, and guiding execution of the bone resection.

Abstract: A magnetic component includes a core, a winding, a lead frame and a conductive material. The winding is disposed in the core. A winding end of the winding extends to an outer periphery of the core. The lead frame is disposed on the outer periphery of the core. At least one hole is formed on the lead frame and corresponds to the winding end. The conductive material is disposed in the at least one hole. The conductive material is in contact with the winding end.

Abstract: Methods and devices of having an enclosure structure formed in a multi-layer interconnect and a through-silicon-via (TSV) extending through the enclosure structure. In some implementations, a protection layer is formed between the enclosure structure and the TSV.

Abstract: Provided is an array substrate. The array substrate includes at least one pad group disposed in a peripheral region of a base substrate, wherein the at least one pad group includes a sector pad group in which the pads are distributed in a sector shape. Therefore, the bonding yield between the array substrate and the circuit board is increased.

Abstract: A nanosheet diode includes a bookend structure and a central structure. The bookend includes a first semiconductor that is doped as one of the anode and the cathode of the diode, and includes a left block, a right block, and a first stack of spaced-apart nanosheets that horizontally connect the left and right blocks. The central structure includes a second semiconductor that is doped as the other of the anode and the cathode of the diode, and includes a front block, a rear block, and a second stack of nanosheets that are interleaved crosswise into spaces between the first stack of spaced-apart nanosheets and that horizontally connect the front and rear blocks. The bookend structure directly contacts top, bottom, and end surfaces of the second stack of nanosheets of the central structure.

Abstract: Some embodiments of the present disclosure relate to an integrated chip including an extended via that spans a combined height of a wire and a via and that has a smaller footprint than the wire. The extended via may replace a wire and an adjoining via at locations where the sizing and the spacing of the wire are reaching lower limits. Because the extended via has a smaller footprint than the wire, replacing the wire and the adjoining via with the extended via relaxes spacing and allows the size of the pixel to be further reduced. The extended via finds application for capacitor arrays used for pixel circuits.

Abstract: A semiconductor includes a first GAA FET and second GAA FET. The second GAA FET includes a first gate dielectric and second gate dielectric within its gate structure. The first GAA FET includes just the first gate dielectric within its gate structure. The gate dielectric structure of the first GAA FET provides for a nominal or a lesser effective gate dielectric or gate dielectric resistance relative to an effective gate dielectric structure of the second GAA FET. The first GAA FET further includes a first gate conductor within its gate structure and the second GAA FET further includes the first gate conductor and a second gate conductor within its gate structure. The first gate conductor and the second gate conductor are separated by the second gate dielectric.

Abstract: A semiconductor structure having a backside contact structure with increased contact area includes a plurality of source/drain regions within a field effect transistor, each of the plurality of source/drain regions includes a top portion having an inverted V-shaped area. A backside power rail is electrically connected to at least one source/drain region through a backside metal contact. The backside metal contact wraps around a top portion of the at least one source/drain region. A tip of the top portion of the plurality of source/drain regions points towards the backside power rail with the top portion of the at least one source/drain region being in electric contact with the backside metal contact. A first epitaxial layer is in contact with a top portion of at least another source/drain region adjacent to the at least one source/drain region for electrically isolating the at least another source/drain region from the backside power rail.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an interconnection structure over a semiconductor substrate and a conductive pillar over the interconnection structure. The conductive pillar has a protruding portion extending towards the semiconductor substrate from a lower surface of the conductive pillar. The semiconductor device structure also includes an upper conductive via between the conductive pillar and the interconnection structure and a lower conductive via between the upper conductive via and the interconnection structure. The lower conductive via is electrically connected to the conductive pillar through the upper conductive via. The conductive pillar extends across opposite sidewalls of the upper conductive via and opposite sidewalls of the lower conductive via. A top view of an entirety of the second conductive via is separated from a top view of an entirety of the protruding portion.

Abstract: A lower set of semiconductor channel layers, an upper set of semiconductor channel layers, a lower dielectric layer adjacent to the lower set of semiconductor channel layers, the lower dielectric layer includes a first polarity stress on the lower set of semiconductor channel layers, and an upper dielectric layer adjacent to the upper set of semiconductor channel layers, the lower dielectric layer includes a second polarity stress on the upper set of semiconductor channel layers with opposite polarity stress of the first polarity stress. Forming a lower stack of nanosheet layers and an upper stack of nanosheet layers, forming a lower dielectric layer adjacent to the lower stack of nanosheet layers, the lower dielectric layer includes a first polarity stress, and forming an upper dielectric layer adjacent to the upper stack of nanosheet layers, the upper dielectric layer includes a second polarity stress with opposite polarity.

Abstract: The present invention relates to a method for preparing glufosinate or an analogue and an intermediate thereof. The method comprises: a) reacting a compound of formula (II), an alcohol of formula (III) and a compound of formula (V); and b) hydrolyzing the product of the reaction above to obtain glufosinate of formula (IV) or an analogue thereof.

Abstract: A thin film transistor includes a gate electrode embedded in an insulating layer that overlies a substrate, a gate dielectric overlying the gate electrode, an active layer comprising a compound semiconductor material and overlying the gate dielectric, and a source electrode and drain electrode contacting end portions of the active layer. The gate dielectric may have thicker portions over interfaces with the insulating layer to suppress hydrogen diffusion therethrough. Additionally or alternatively, a passivation capping dielectric including a dielectric metal oxide material may be interposed between the active layer and a dielectric layer overlying the active layer to suppress hydrogen diffusion therethrough.

Abstract: Provided are a package structure and a method of forming the same. The method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.

Abstract: Some implementations described herein provide an exposure tool. The exposure tool includes a reticle deformation detector and one or more processors configured to obtain, via the reticle deformation detector, reticle deformation information associated with a reticle during a scanning process for scanning multiple fields of a wafer. The one or more processors determine, based on the reticle deformation information, a deformation of the reticle at multiple times during the scanning process, and perform, based on the deformation of the reticle at the multiple times, one or more adjustments of one or more components of the exposure tool during the scanning process.

Abstract: A semiconductor device including a substrate having a dense array region and an isolation region. The semiconductor device includes plurality of first fin structures of stacked nanosheets is present in the dense array region separated by a single pitch, wherein each fin structure in the first plurality of fin structures has a same first nanosheet height as measured from an upper surface of the substrate in the dense array region. The semiconductor device further includes at least one second fin structure of stacked nanosheets is present in the isolation region, wherein a number of second fin structure in the isolation region is less than a number of first fin structures in the dense array region, the at least one fin structure having a second nano sheet height that is measured from the upper surface of the substrate in the isolation region that is the same as the first nanosheet height.

Abstract: A scan-type display apparatus includes an LED array and a scan driver. The LED array has a common anode configuration, and includes multiple scan lines, multiple data lines and multiple LEDs. The scan driver includes multiple scan driving circuits. Each scan driving circuit includes a voltage generator and a detector. The voltage generator has an output terminal that is connected to the scan line corresponding to the scan driving circuit, and is configured to output one of an input voltage and a clamp voltage at the output terminal of the voltage generator. The detector is connected to the output terminal of the voltage generator, and generates a detection signal that indicates whether any one of the LEDs connected to the scan line corresponding to the scan driving circuit is short circuited based on a voltage at the output terminal of the voltage generator and a detection timing signal.

Abstract: The present disclosure provides a particle size statistical method of granular minerals of shale, comprising: collecting shale samples; cutting the collected samples into the size of 1 cm×1 cm×1 cm; performing argon ion polishing; magnifying the samples by the field emission scanning electron microscopy, collecting 500-1000 images; using Adobe Photoshop to seamlessly splice the collected images; using ImageJ in combination with EDS energy spectrum to determine types of mineral particles, performing background subtraction, and setting a reasonable grayscale threshold to classify the particle minerals; performing binary processing on the images of selected mineral particle types; identifying edges of granular minerals, and using a Analyze Particles command to statistically analyze and measure particle sizes, and drawing a particle size distribution histogram.

Abstract: An electronic component includes a board, an electronic device, and a stiffening structure is provided. The electronic device is disposed on the board. The stiffening structure is disposed on the board. The stiffening structure includes a ring portion corresponding the edge of the board. The stiffening structure includes a core base and a cladding layer. The cladding layer covers the core base.

Abstract: A method includes transferring a wafer to a position over a wafer chuck; lifting a lifting pin through the wafer chuck to a first position to support the wafer; holding the wafer on the lifting pin using a negative pressure source in gaseous communication with an inner gas passage of the lifting pin; introducing a gas to a region between the wafer and the wafer chuck through an outer gas passage of the lifting pin, wherein in a top view of the lifting pin, the inner gas passage has a circular profile, while the outer gas passage has a ring-shape profile; and lowering the lifting to dispose the wafer over the wafer chuck.

Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.