Abstract: Provided herein may be a semiconductor memory device that may include a plurality of memory blocks configured to share bit lines and a common source line, a voltage generation circuit configured to apply an erase voltage to the common source line, and operation voltages to word lines and select lines of the plurality of memory blocks during an erase operation, a read and write circuit configured to check a program and erase status of an unselected memory block of the plurality of memory blocks during the erase operation, and a control logic configured to control the voltage generation circuit so that the operation voltages applied to select lines of a selected memory block are controlled in accordance with a result of checking the program and erase status of the unselected memory block during the erase operation.

Abstract: A voltage generator which generates an internal voltage based on a varying voltage derived from the internal voltage includes a feedback control circuit configured to variably transmit the varying voltage responsive to a control signal to generate a feedback voltage. A voltage generation circuit is configured to generate the internal voltage based on the feedback voltage.

Abstract: A semiconductor memory device includes bank arrays, row decoders, column decoders, a timing control circuit and repeaters. The bank arrays are distributed in a core region of a substrate, and each bank array includes sub-array blocks and includes a plurality of memory cells coupled to a plurality of word-lines and a plurality of bit-lines. Each row decoder is disposed adjacent each bank array in a first direction. Each column decoder is disposed adjacent each bank array in a second direction. The timing control circuit, which is disposed in a peripheral region of the substrate, generates a first control signal to control the word-lines and a second control signal to control the bit-lines in response to operation control signals. Each repeater is disposed adjacent each column decoder and each repeater transfers the first and second control signals to the sub-array blocks in the second direction.

Abstract: A multi-chip package includes a first die having temperature sensors and a second die. The first die generates temperature deviation information of m (m<n) bits based on temperature information of n bits produced by the temperature sensors. The first die provides the temperature deviation information of m bits rather than the temperature information of n bits to the second die. An internal operation of the second die is controlled using the temperature deviation information output by the first die.

Abstract: Provided herein may be a semiconductor memory device that may include a plurality of memory blocks configured to share bit lines and a common source line, a voltage generation circuit configured to apply an erase voltage to the common source line, and operation voltages to word lines and select lines of the plurality of memory blocks during an erase operation, a read and write circuit configured to check a program and erase status of an unselected memory block of the plurality of memory blocks during the erase operation, and a control logic configured to control the voltage generation circuit so that the operation voltages applied to select lines of a selected memory block are controlled in accordance with a result of checking the program and erase status of the unselected memory block during the erase operation.

Abstract: A semiconductor memory device may include a control logic. The control logic may be coupled to bit lines through a read and write (read/write) circuit and to word lines. The control logic is configured to determine a duration of an activation time of a strobe signal for the read/write circuit.

Abstract: A multi-chip package includes a first die having temperature sensors and a second die. The first die generates temperature deviation information of m (m<n) bits based on temperature information of n bits produced by the temperature sensors. The first die provides the temperature deviation information of m bits rather than the temperature information of n bits to the second die. An internal operation of the second die is controlled using the temperature deviation information output by the first die.

Abstract: A method is provided for programming a non-volatile memory having a plurality of word lines, the method comprising: applying a pass voltage to a selected word line among the plurality of word lines; and applying one of first and second program voltages to the selected word line by increasing the pass voltage, wherein the applying of one of the first and second program voltages increases the pass voltage with a single increment.

Abstract: Provided herein may be a semiconductor memory device that may include a plurality of memory blocks configured to share bit lines and a common source line, a voltage generation circuit configured to apply an erase voltage to the common source line, and operation voltages to word lines and select lines of the plurality of memory blocks during an erase operation, a read and write circuit configured to check a program and erase status of an unselected memory block of the plurality of memory blocks during the erase operation, and a control logic configured to control the voltage generation circuit so that the operation voltages applied to select lines of a selected memory block are controlled in accordance with a result of checking the program and erase status of the unselected memory block during the erase operation.

Abstract: A semiconductor memory device includes bank arrays, row decoders, column decoders, a timing control circuit and repeaters. The bank arrays are distributed in a core region of a substrate, and each bank array includes sub-array blocks and includes a plurality of memory cells coupled to a plurality of word-lines and a plurality of bit-lines. Each row decoder is disposed adjacent each bank array in a first direction. Each column decoder is disposed adjacent each bank array in a second direction. The timing control circuit, which is disposed in a peripheral region of the substrate, generates a first control signal to control the word-lines and a second control signal to control the bit-lines in response to operation control signals. Each repeater is disposed adjacent each column decoder and each repeater transfers the first and second control signals to the sub-array blocks in the second direction.

Abstract: The present disclosure memory includes a controller for a semiconductor memory device, the device including a memory cell array including a plurality of pages. The controller includes a memory control module suitable for translating a logical address for data provided from a host to a physical address representing one of the plurality of pages, and determining one of a plurality of operation modes based on the physical address and pre-stored parity-related information. The controller further includes and an error correction code circuit suitable for generating parity-data for the data provided from the host according to the determined operation mode.

Abstract: Provided herein is a semiconductor memory device and an operating method thereof. The semiconductor memory device includes a memory cell array and a control logic. The memory cell array includes a plurality of memory blocks. The control logic groups the memory blocks, determines driving voltages to be respectively applied to the groups, and applies each of the determined driving voltages to memory blocks included in a corresponding group to control the operation of the memory cell array.

Abstract: There are provided a semiconductor memory device and an operating method thereof. A semiconductor memory device may include a memory cell array, a peripheral circuit, a control logic, and one or more programs. The memory cell array may include a plurality of memory cells. The peripheral circuit may perform a program operation on the memory cell array. The control logic may control the peripheral circuit to program the memory cell array. The one or more programs are configured to be executed by the control logic. The programs may include an instruction for pre-programming one or more memory cells to be programmed to one or more target program states to have threshold voltage distributions lower than the target program state.

Abstract: A separator for a battery interposed between a cathode and an anode, and a method of manufacturing the same are provided, the separator for a lithium ion secondary battery including a porous polymer sheet having a first surface and a second surface opposing the first surface, and in which a pore communicating the first surface and the second surface is formed, and a heat resistant inorganic material layer coating at least the first surface and a surface of the pore, and formed in an atomic layer deposition method, wherein the heat resistant inorganic material layer formed on the first surface or the second surface has a thickness of 20 nm to 100 nm, porosity of the separator after the heat resistant inorganic material layer is formed is 30% to 70%, and a gurley value is 100 s/100 ml to 1000 s/100 ml.

Abstract: A voltage generator which generates an internal voltage based on a varying voltage derived from the internal voltage includes a feedback control circuit configured to variably transmit the varying voltage responsive to a control signal to generate a feedback voltage. A voltage generation circuit is configured to generate the internal voltage based on the feedback voltage.

Abstract: Provided is a porous separator for a secondary battery including an inorganic oxide layer formed on a porous substrate by an atomic layer deposition process, such that a thin separator having excellent heat stability, permeability and electrolyte impregnability may be provided by controlling specific conditions in the process and thicknesses of the inorganic oxide layers on a surface and inside of the porous separator.

Abstract: A multi-chip package includes a first die having temperature sensors and a second die. The first die generates temperature deviation information of m (m<n) bits based on temperature information of n bits produced by the temperature sensors. The first die provides the temperature deviation information of m bits rather than the temperature information of n bits to the second die. An internal operation of the second die is controlled using the temperature deviation information output by the first die.

Abstract: There are provided a semiconductor memory device and an operating method thereof. A semiconductor memory device may include a memory cell array, a peripheral circuit, a control logic, and one or more programs. The memory cell array may include a plurality of memory cells. The peripheral circuit may perform a program operation on the memory cell array. The control logic may control the peripheral circuit to program the memory cell array. The one or more programs are configured to be executed by the control logic. The programs may include an instruction for pre-programming one or more memory cells to be programmed to one or more target program states to have threshold voltage distributions lower than the target program state.

Abstract: A multi-chip package includes a first die having temperature sensors and a second die. The first die generates temperature deviation information of m (m<n) bits based on temperature information of n bits produced by the temperature sensors. The first die provides the temperature deviation information of m bits rather than the temperature information of n bits to the second die. An internal operation of the second die is controlled using the temperature deviation information output by the first die.

Abstract: A stacked semiconductor device includes a plurality of semiconductor dies and a plurality of thermal-mechanical bumps. The semiconductor dies are stacked in a vertical direction. The thermal-mechanical bumps are disposed in bump layers between the semiconductor dies. Fewer thermal-mechanical bumps are disposed at a location near a heat source included in the semiconductor dies than at other locations, or a structure of the thermal-mechanical bumps at the location near the heat source is different from a structure of the thermal-mechanical bumps at other locations.