Abstract: A separator for a secondary cell includes a porous polymer substrate having a first surface, a second surface opposing the first surface, and a plurality of pores connecting the first surface to the second surface; and heat-resistant coating layers formed on at least one of the first surface and the second surface of the porous polymer substrate and on internal surfaces of the pores using an atomic layer deposition process (ALD). Pores having a non-coated region are present in the internal surfaces of the pores.

Abstract: A separator for a secondary battery includes a porous polymer sheet having a first surface, a second surface opposing the first surface, and a plurality of pores connecting the first surface to the second surface; and heat-resistant inorganic layers formed on at least one of the first surface or the second surface of the porous polymer sheet and on internal surfaces of the pores using an atomic layer deposition (ALD) process. The at least one of the first surface or the second surface and the internal surfaces of the pores have hydrophobically coated hydrophobic layers having hydrophobic functional groups on the heat-resistant inorganic layers.

Abstract: A memory device with separated capacitors is realized as a multi-chip package in which a first die and a second die are stacked. The first die may be a memory die including a first circuit connected to a memory cell array and driven by a first power voltage and a first ground voltage. A first capacitor may be connected between the first power and ground voltages. The second die may be a capacitor die stacked on the first die and including a second capacitor connected in parallel to the first capacitor of the first die via through-substrate-vias (TSVs).

Abstract: The semiconductor device includes a memory block including programmed pages and non-programmed pages, a peripheral circuit configured to perform a read operation of the memory block, and a control circuit configured to control the peripheral circuit so that a read voltage is applied to a word line coupled to a selected page among the pages for the read operation, a first pass voltage is applied to word lines coupled to the programmed pages among pages that are not selected for the read operation, and a second pass voltage lower than the first pass voltage is applied to word lines coupled to non-programmed pages among the pages that are not selected for the read operation.

Abstract: A method of operating a semiconductor memory device includes performing a first program operation to simultaneously increase threshold voltages of memory cells having different target levels to sub-levels lower than the different target levels, verifying the memory cells by using different verify voltages, respectively, performing a second program operation to divide the threshold voltages of the memory cells, and performing a third program operation to increase the threshold voltages of the memory cells to the different target levels, respectively.

Abstract: The present disclosure memory includes a controller for a semiconductor memory device, the device including a memory cell array including a plurality of pages. The controller includes a memory control module suitable for translating a logical address for data provided from a host to a physical address representing one of the plurality of pages, and determining one of a plurality of operation modes based on the physical address and pre-stored parity-related information. The controller further includes and an error correction code circuit suitable for generating parity-data for the data provided from the host according to the determined operation mode.

Abstract: The semiconductor device includes a memory block including programmed pages and non-programmed pages, a peripheral circuit configured to perform a read operation of the memory block, and a control circuit configured to control the peripheral circuit so that a read voltage is applied to a word line coupled to a selected page among the pages for the read operation, a first pass voltage is applied to word lines coupled to the programmed pages among pages that are not selected for the read operation, and a second pass voltage lower than the first pass voltage is applied to word lines coupled to non-programmed pages among the pages that are not selected for the read operation.

Abstract: A method is provided for programming a non-volatile memory having a plurality of word lines, the method comprising: applying a pass voltage to a selected word line among the plurality of word lines; and applying one of first and second program voltages to the selected word line by increasing the pass voltage, wherein the applying of one of the first and second program voltages increases the pass voltage with a single increment.

Abstract: A memory system includes a semiconductor memory device including memory cells and an internal Random Access Memory (RAM); and a controller suitable for transmitting read retry table information to the semiconductor memory device when a read operation for the memory cells fails, wherein the internal RAM stores a read retry table during operation of the memory system, and wherein the semiconductor memory device performs a read retry operation with a read retry voltage determined based on the read retry table and the read retry table information.

Abstract: A method of operating a semiconductor memory device includes performing a first program operation to simultaneously increase threshold voltages of memory cells having different target levels to sub-levels lower than the different target levels, verifying the memory cells by using different verify voltages, respectively, performing a second program operation to divide the threshold voltages of the memory cells, and performing a third program operation to increase the threshold voltages of the memory cells to the different target levels, respectively.

Abstract: A multi-chip package includes a first die having temperature sensors and a second die. The first die generates temperature deviation information of m (m<n) bits based on temperature information of n bits produced by the temperature sensors. The first die provides the temperature deviation information of m bits rather than the temperature information of n bits to the second die. An internal operation of the second die is controlled using the temperature deviation information output by the first die.

Abstract: An injection molding apparatus is usable in an injection machine to form an injection product. The slim injection molding apparatus includes a hot runner plate attachable to one side clamping plate of the injection machine and provided with a hot runner system; an upper core disposed in the hot runner plate; a lower core attachable to an opposite side clamping plate of the injection machine to face the upper core, the lower core configured to couple with the upper core to define a cavity corresponding to the injection product when the lower core is coupled to the upper core; and an ejecting core disposed in the lower core, the ejecting core configured to push the injection product upward when the upper core is separated from the lower core.

Abstract: A method of operating a semiconductor memory device includes performing a first program operation to simultaneously increase threshold voltages of memory cells having different target levels to sub-levels lower than the different target levels, verifying the memory cells by using different verify voltages, respectively, performing a second program operation to divide the threshold voltages of the memory cells, and performing a third program operation to increase the threshold voltages of the memory cells to the different target levels, respectively.

Abstract: Provided is a method of detecting a concentrated address of a semiconductor device using an n-bit address. The method includes dividing the n-bit address into k groups, wherein each of n and k is an integer equal to or greater than 2, for each group of the k groups, detecting one or more concentrated sub addresses corresponding to the group, and generating at least one concentrated address by combining the one or more concentrated sub addresses for the k groups.

Abstract: Provided is a cellulose acylate film for an optical film usable for optical compensation sheet, an optical filter for stereoscopic images, a polarizer and a liquid crystal display and the like.

Abstract: A semiconductor memory device and methods thereof are provided. The example semiconductor memory device may include an internal address generating circuit operating in accordance with a first addressing protocol during normal operation and operating in accordance with a second addressing protocol during a test operation, the first addressing protocol associated with a first number of clock cycles for transferring a memory address and the second addressing protocol associated with a second number of clock cycles for transferring a memory address, the first number of clock cycles being greater than the second number of clock cycles.

Abstract: A liquid crystal display comprises a lower substrate, multiple seal patterns formed on the lower substrate and including spacers and sealant, and an upper substrate sealed by the multiple seal patterns. Spacers of one seal pattern, formed on wiring, of the multiple seal patterns comprise conductive spacers so that conductivity is improved while a cell gap between two substrates is stably maintained by sealing the substrates using a conductive seal pattern and a seal pattern for maintaining the gap. Furthermore, the liquid crystal display is capable of maintaining a cell gap between the two substrates more stably by forming black matrices on a front surface of the substrate in a pixel region of the liquid crystal display, thereby relieving a bump on the upper substrate.

Abstract: A liquid crystal display (LCD) capable of preventing spots from being generated by difference in brightness caused by variation in a gap between substrates is provided. The LCD includes a first pad unit positioned on an upper corner of a lower substrate, a second pad unit positioned on a lower corner of the lower substrate diagonally across from the first pad unit, an integrated circuit electrically connected to the first pad unit and the second pad unit, and dummy pads positioned on the other upper corner of the lower substrate. The dummy pads are substantially symmetrical with second pads included in the second pad unit thus helping maintain the gap between the substrates uniform.

Abstract: Provided is a circuit for setting an optimized condition of a semiconductor circuit including a fuse cut signal generator configured to generate a fuse cut signal in response to a first control signal, and a state setting circuit configured to generate an optimization signal in response to a plurality of state control signals and the fuse cut signal.

Abstract: A data input/output circuit of a semiconductor memory device has a data inversion determination function. In an input mode, the data input/output circuit inverts an input data group in response to an input inversion flag and transmits the inverted input data group to a memory cell array. In an output mode, the data input/output circuit inverts a data group, output from the memory cell array, when the output data group satisfies a predetermined inversion condition, and transmits the inverted output data group to the outside of the data input/output circuit. In this case, an output inversion flag, indicating that the output data group is to be inverted, is generated. Further, the data input/output circuit stores the input inversion flag in the memory cell array in the input mode, and compares the input inversion flag, stored in the memory cell array, with the output inversion flag in the output mode.