Abstract: A method includes providing a structure having a substrate and a channel layer over the substrate; forming a high-k gate dielectric layer over the channel layer; forming a work function metal layer over the high-k gate dielectric layer; forming a silicide layer over the work function metal layer; annealing the structure such that a first portion of the work function metal layer that interfaces with the high-k gate dielectric layer is doped with silicon elements from the silicide layer; removing the silicide layer; and forming a bulk metal layer over the work function metal layer.

Abstract: An exhaust gas heating system is provided, comprising a first end face, a second end face, a plurality of honeycomb segments, and a plurality of electrically nonconductive layers. Each honeycomb segment comprises an array of intersecting walls forming channels extending axially between the first end face and the second end face. The intersecting walls comprise an electrically conductive material. The heater further comprises a plurality of electrically nonconductive layers arranged between adjacent segments of the honeycomb segments. The arrays of intersecting walls of the honeycomb segments are electrically isolated from each other by the nonconductive layers. The exhaust gas heating system further comprises a coil wrapped around an external surface of the heater arranged between the first end face and the second end face. The exhaust gas heating system further comprises a DC to AC converter configured to supply the coil with an AC current.

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.

Abstract: A memory circuit includes a memory array including a plurality of memory cells, each memory cell including a gate structure including a ferroelectric layer and a channel layer adjacent to the gate structure, the channel layer including a metal oxide material. A driver circuit is configured to output a gate voltage to the gate structure of a memory cell, the gate voltage having a positive polarity and a first magnitude in in a first write operation and a negative polarity and a second magnitude in in a second write operation, and to control the second magnitude to be greater than the first magnitude.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a channel member including a first channel layer and a second channel layer over the first channel layer, and a gate structure over the channel member. The first channel layer includes silicon, germanium, a III-V semiconductor, or a II-VI semiconductor and the second channel layer includes a two-dimensional material.

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a channel member including a first channel layer and a second channel layer over the first channel layer, and a gate structure over the channel member. The first channel layer includes silicon, germanium, a III-V semiconductor, or a II-VI semiconductor and the second channel layer includes a two-dimensional material.

Abstract: The present disclosure provides methods and compositions for the treatment, identification, diagnosis, and prognosis of dystonia, or dystonia related disorders.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The first nanostructure has a first channel direction, and the first channel direction is [1 0 0], [?1 0 0], [0 1 0], or [0 ?1 0]. The semiconductor device structure includes a gate stack over the substrate and surrounding the first nanostructure. The semiconductor device structure includes a first source/drain structure and a second source/drain structure over the substrate and over opposite sides of the gate stack.

Abstract: A honeycomb extrusion die (120) includes a die body (342) including an inlet face (315) and an outlet face (341). A plurality of pins (330) extend from the die body (342), wherein the pins (330) are arranged to define primary (312P) and secondary slots (312S). Primary slots (312P) include primary slot inlets (320P) and primary slot outlets (3120) and the secondary slots (312S) include secondary slot inlets (312SI) and secondary slot outlets (312SO). Feedholes (317) extend within the die body (342), the feedholes (317) including feedhole outlets (319), wherein the feedhole outlets (319) intersect only with the primary slot inlets (320P). First surface indentation features (345) extend into side surfaces (332) of the plurality of pins (330) defining the primary slots (312P). The first surface indentation features (345) are spaced from the primary slot outlets (3120). The secondary slots (312S) are devoid of surface indentation features. Other die bodies, extruders, and methods are disclosed.

Abstract: A semiconductor device includes a semiconductor substrate, an interfacial layer formed on the semiconductor substrate, a high-k dielectric layer formed on the interfacial layer, and a conductive gate electrode layer formed on the high-k dielectric layer. At least one of the high-k dielectric layer and the interfacial layer is doped with: a first dopant species, a second dopant species, and a third dopant species. The first dopant species and the second dopant species form a plurality of first dipole elements having a first polarity. The third dopant species forms a plurality of second dipole elements having a second polarity, and the first and second polarities are opposite.

Abstract: A data processing method for detection of deterioration of semiconductor process kits includes the following steps: acquiring a plurality of Raman spectra data of a semiconductor process kit and performing a plurality calculating processes on the Raman spectra data to obtain a first deterioration state determining parameter indicating the aging degree of the entire semiconductor process kit and a second deterioration state determining parameter indicating the degree of variation of the internal molecular structure of the semiconductor process kit.

Abstract: An example electronic device includes a controller to determine a user touch detection by a power adaptor coupled to the electronic device to operate the electronic device in an AC power mode. The power adaptor may comprise a proximity sensor to detect a user touch for detachment of the power adaptor from the electronic device, and a control circuit to operate a configuration pin in a low output mode to signal user touch detection. The controller may initiate central processing unit (CPU) throttling to reduce power consumption by the electronic device. The controller may further stop CPU throttling in response to detecting that the power adaptor has been detached from the electronic device. Further, the controller may switch the electronic device to a DC power mode to operate using DC power supplied by a battery of the electronic device in response to power adaptor detachment.

Abstract: The present disclosure provides low resistance contacts and damascene interconnects with one or more graphene layers in fin structures of FETs. An example semiconductor device can include a substrate with a fin structure that includes an epitaxial region. The semiconductor device can also include an etch stop layer on the epitaxial region, and an interlayer dielectric layer on the etch stop layer. The semiconductor device can further include a metal contact, above the epitaxial region, formed through the etch stop layer and the interlayer dielectric layer, and a graphene film at interfaces between the metal contact and each of the epitaxial region, the etch stop layer, and the interlayer dielectric layer.

Abstract: A method includes providing a structure having a substrate and a channel layer over the substrate; forming a high-k gate dielectric layer over the channel layer; forming a work function metal layer over the high-k gate dielectric layer; forming a silicide layer over the work function metal layer; annealing the structure such that a first portion of the work function metal layer that interfaces with the high-k gate dielectric layer is doped with silicon elements from the silicide layer; removing the silicide layer; and forming a bulk metal layer over the work function metal layer.

Abstract: Systems and methods for allocating resources. The system includes a communications module, a processor, and a memory. The memory stores a data record and instructions that, when executed, configure the processor to obtain a data record and transmit an existing score indication corresponding to the data record for display at the client device; receive a first time parameter and an action indicator associated with a shared resource and, in response, determine a first provisional score corresponding to the data record based on the existing score indication, the action indicator, and the first time parameter to provide a first provisional score indication; transmit the first provisional score indication and a selectable option associated with the action indicator for display at the client device while the first provisional score indication is displayed; and in response to receiving a resource transfer instruction, allocate the shared resource associated with the action indicator.

Abstract: A method includes forming a fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over a substrate. A dummy gate structure is formed across the fin structure. The exposed second portions of the fin structure are removed. A selective etching process is performed, using a gas mixture including a hydrogen-containing gas and a fluorine-containing gas, to laterally recess the first semiconductor layers. Inner spacers are formed on opposite end surfaces of the laterally recessed first semiconductor layers. Source/drain epitaxial structures are formed on opposite end surfaces of the second semiconductor layers. The dummy gate structure is removed to expose the first portion of the fin structure. The laterally recessed first semiconductor layers are removed. A gate structure is formed to surround each of the second semiconductor layers.

Abstract: The present invention relates to a processing method for coating glass container with silicone rubber and a glass container coated with silicone rubber by the processing method. The processing method comprises: cleaning a glass container body and performing a first drying treatment; brushing or spraying a primer on a surface of a part of the glass container body, wherein the surface of the part of the glass container body is to be coated with silicone rubber; performing a second drying treatment on the glass container body, and then cooling the glass container body to a room temperature; putting the glass container body into a mold cavity of a mold, injecting the liquid silicone rubber into the mold cavity, and vulcanizing the liquid silicone rubber for 200 to 300 seconds; opening the mold and letting the mold sliding out, and taking out the glass container coated with the silicone rubber layer.

Abstract: A deterioration detecting system for semiconductor process kits has a Raman spectrometer, an optical detecting unit, a Raman spectra database unit, and a controlling-computing unit. The optical detecting unit and the controlling-computing unit are both coupled to the Raman spectrometer. The Raman spectrometer detects a semiconductor process kit under detection through the optical detecting unit to obtain a scatter light having an excited Raman spectrum signal. The Raman spectra database unit stores a plurality of Raman spectrum signals corresponding to multiple known use hours, multiple known materials, multiple known material compounds, or multiple known material deterioration state, of the semiconductor process kit under detection.

Abstract: A semiconductor package includes a first chip and a second chip arranged side by side on a carrier substrate. The first chip is provided with a high-speed signal pads along a first side in proximity to the second chip. The second chip includes a redistribution layer, and the redistribution layer is provided with data (DQ) pads along the second side in proximity to the first chip. A plurality of first bonding wires is provided to directly connect the high-speed signal pads to the DQ pads. The redistribution layer of the second chip is provided with first command/address (CA) pads along the third side opposite to the second side, and a plurality of dummy pads corresponding to the first CA pads. The plurality of dummy pads are connected to second CA pads disposed along a fourth side of the second chip via interconnects of the redistribution layer.