Patents by Inventor Min Shen

Min Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11292152
    Abstract: An extrusion die (100) for a honeycomb body, the die (100) including: an input surface (102); an opposing output surface (104); feed holes (108) extending from the input surface (102) toward the output surface (104); discharge slots (106) having a slot width (SW) and a slot length (SL), and extending from the output surface (104) toward the input surface (102); and a plenum (130) fluidly connecting the feed holes (108) and the discharge slots (106). The plenum (130) may include chambers (132) connected to the feed holes (108) and including tapered outlets (134) connected to the discharge slots (106). The plenum (133) may include first chambers (132A) connected to the feed holes (108) and including first tapered outlets (134A), and second chambers (132B) connected to the first outlets and including second tapered outlets (134B) connected to the discharge slots (106).
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: April 5, 2022
    Assignee: Corning Incorporated
    Inventors: Thomas William Brew, Tushar Gulati, Lee James Parks, Min Shen
  • Patent number: 11285142
    Abstract: The present disclosure provides methods and compositions for the treatment, identification, diagnosis, and prognosis of dystonia, or dystonia related disorders.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: March 29, 2022
    Assignees: The United States of America, as Represented by the Secretary, Department of Health and Human Services, Duke University
    Inventors: Nicole Calakos, Zachary F. Caffall, Joseph Rittiner, Min Shen, Jennifer T. Fox, Zhuyin Li
  • Publication number: 20220056579
    Abstract: Methods of depositing an inorganic material on an extrusion die including positioning an extrusion die within a vapor deposition chamber, positioning an impedance disk over a face of the extrusion die, the impedance disk having a plurality of through holes and the face of the extrusion die having a plurality of slots defined by a plurality of extrusion die pins, and flowing one or more deposition gases through the plurality of through holes and into the plurality of slots to deposit inorganic particles on side walls of the plurality of pins. The total impedance to the flow of the deposition gases across the impedance disk and the extrusion die may be equal to a disk impedance of the impedance disk plus a die impedance of the extrusion die, and the disk impedance may be at least 40% of the total impedance to the flow of the deposition gases.
    Type: Application
    Filed: December 13, 2019
    Publication date: February 24, 2022
    Inventors: Thomas William Brew, Yuehao Li, Min Shen
  • Publication number: 20220045176
    Abstract: Semiconductor devices and methods of forming the same are provided. A method includes providing a workpiece having a semiconductor structure; depositing a two-dimensional (2D) material layer over the semiconductor structure; forming a source feature and a drain feature electrically connected to the semiconductor structure and the 2D material layer, wherein the source feature and drain feature include a semiconductor material; and forming a gate structure over the two-dimensional material layer and interposed between the source feature and the drain feature. The gate structure, the source feature, the drain feature, the semiconductor structure and the 2D material layer are configured to form a field-effect transistor. The semiconductor structure and the 2D material layer function, respectively, as a first channel and a second channel between the source feature and the drain feature.
    Type: Application
    Filed: March 31, 2021
    Publication date: February 10, 2022
    Inventors: Dhanyakumar Mahaveer Sathaiya, Khaderbad Mrunal Abhijith, Tzer-Min Shen
  • Publication number: 20220045188
    Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.
    Type: Application
    Filed: January 7, 2021
    Publication date: February 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsu-Kai Chang, Jhih-Rong Huang, Yen-Tien Tung, Chia-Hung Chu, Shuen-Shin Liang, Tzer-Min Shen, Pinyen Lin, Sung-Li Wang
  • Publication number: 20220034814
    Abstract: A deterioration detecting system for semiconductor process kits has a Raman spectrometer, an optical detecting unit, a Raman spectra database unit, and a controlling-computing unit. The optical detecting unit and the controlling-computing unit are both coupled to the Raman spectrometer. The Raman spectrometer detects a semiconductor process kit under detection through the optical detecting unit to obtain a scatter light having an excited Raman spectrum signal. The Raman spectra database unit stores a plurality of Raman spectrum signals corresponding to multiple known use hours, multiple known materials, multiple known material compounds, or multiple known material deterioration state, of the semiconductor process kit under detection.
    Type: Application
    Filed: September 24, 2020
    Publication date: February 3, 2022
    Inventors: Chyuan-Ruey LIN, Feng-Min SHEN, Hung-Chia SU
  • Publication number: 20220037500
    Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a gate structure disposed on the fin structure, a source/drain (S/D) region disposed adjacent to the gate structure, a contact structure disposed on the S/D region, and a dipole layer disposed at an interface between the ternary compound layer and the S/D region. The contact structure includes a ternary compound layer disposed on the S/D region, a work function metal (WFM) silicide layer disposed on the ternary compound layer, and a contact plug disposed on the WFM silicide layer.
    Type: Application
    Filed: March 10, 2021
    Publication date: February 3, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sung-Li WANG, Hsu-Kai CHANG, Jhih-Rong HUANG, Yen-Tien TUNG, Chia-Hung CHU, Tzer-Min SHEN, Pinyen LIN
  • Publication number: 20220020644
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a first channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure.
    Type: Application
    Filed: January 7, 2021
    Publication date: January 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Yu LIN, Jhih-Rong Huang, Yen-Tien Tung, Tzer-Min Shen, Fu-Ting Yen, Gary Chan, Keng-Chu Lin, Li-Te Lin, Pinyen Lin
  • Patent number: 11225469
    Abstract: The present invention provides compounds of Formula (II), and pharmaceutically acceptable salts, solvates, hydrates, polymorphs, co-crystals, tautomers, stereoisomers, isotopically labeled derivatives, pro-drugs, and compositions thereof. Also provided are methods and kits involving the compounds of Formula (I), (II) or (III) for treating diseases associated with the over-expression of phosphoglycerate dehydrogenase (PHGDH) in a subject, such as proliferative diseases (e.g., cancers (e.g., breast cancer, ER negative breast cancer, melanoma, cervical cancer), benign neoplasms, diseases associated with angiogenesis, inflammatory diseases, autoinflammatory diseases, and autoimmune diseases). Treatment of a subject with a proliferative disease using a compound or composition of the invention may inhibit the activity of PHGDH or inhibit the serine biosynthetic pathway, or both.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: January 18, 2022
    Assignees: Whitehead Institute for Biomedical Research, Dana-Farber Cancer Institute, Inc., The United States of America, as represented by the Secretary, Department of Health and Human Services
    Inventors: David M. Sabatini, Michael Pacold, Matthew B. Boxer, Jason M. Rohde, Kyle R. Brimacombe, Min Shen, Ganesha Bantukallu, Li Liu
  • Patent number: 11201402
    Abstract: A phase shifter assembly includes: a first phase shifter including a first through-hole; a second phase shifter including a second through-hole and disposed at a side of the first phase shifter; a first gear including a third through-hole and disposed at a side of the second phase shifter facing away from the first phase shifter; a rack configured to drive, through driving the first gear, the second phase shifter to move relative to the first phase shifter, to adjust an electrical tilt angle of an antenna corresponding to the phase shifter assembly; and a first reversing mechanism disposed between the first gear and the rack and engaged with the first gear and the rack, respectively, making a direction of a component of a linear velocity at an electrical contact between the first phase shifter and the second phase shifter in a moving direction of the rack is opposite to the moving direction of the rack.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: December 14, 2021
    Assignees: ROSENBERGER TECHNOLOGIES CO., LTD., ROSENBERGER TECHNOLOGIES LLC
    Inventors: Youfang Huangfu, Yongzhong Li, Suyang Bao, Min Shen, Dongfeng Ding, Yang Yang
  • Patent number: 11194812
    Abstract: The disclosed embodiments provide a system for processing data. During operation, the system organizes fact data to be aggregated into sliding time window features and observation data associated with the fact data into a set of partitions based on a join key. Next, the system sorts the fact data and the observation data within the set of partitions by the join key and timestamps associated with the fact data and the observation data. For each observation record in the observation data, the system aggregates fact records in the sorted fact data that share a value of the join key with the observation record and that fall within a first time window associated with the observation record to produce a sliding time window feature. The system then stores the sliding time window feature in association with the observation record.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: December 7, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Min Shen, Maneesh Varshney, David J. Stein, Jian Qiao
  • Publication number: 20210375345
    Abstract: A memory circuit includes a memory array including a plurality of memory cells, each memory cell including a gate structure including a ferroelectric layer and a channel layer adjacent to the gate structure, the channel layer including a metal oxide material. A driver circuit is configured to output a gate voltage to the gate structure of a memory cell, the gate voltage having a positive polarity and a first magnitude in in a first write operation and a negative polarity and a second magnitude in in a second write operation, and to control the second magnitude to be greater than the first magnitude.
    Type: Application
    Filed: March 11, 2021
    Publication date: December 2, 2021
    Inventors: Huan-Sheng WEI, Tzer-Min SHEN, Zhiqiang WU
  • Publication number: 20210327844
    Abstract: A semiconductor package includes a first chip and a second chip arranged side by side on a carrier substrate. The first chip is provided with a high-speed signal pads along a first side in proximity to the second chip. The second chip includes a redistribution layer, and the redistribution layer is provided with data (DQ) pads along the second side in proximity to the first chip. A plurality of first bonding wires is provided to directly connect the high-speed signal pads to the DQ pads. The redistribution layer of the second chip is provided with first command/address (CA) pads along the third side opposite to the second side, and a plurality of dummy pads corresponding to the first CA pads. The plurality of dummy pads are connected to second CA pads disposed along a fourth side of the second chip via interconnects of the redistribution layer.
    Type: Application
    Filed: March 5, 2021
    Publication date: October 21, 2021
    Inventors: Chin-Yuan Lo, Chih-Hao Chang, Tze-Min Shen
  • Publication number: 20210308928
    Abstract: A honeycomb extrusion die (120) includes a die body (302) including an inlet face (306) and an exit face. The die body (302) has slot inlets (309) and a plurality of pins (320, 500) disposed between the slot inlets (309) and the exit face. The plurality of pins (320, 500) include side surfaces (322, 500B) configured to define a matrix of intersecting slots (324), wherein the matrix of intersecting slots (324) has slot exit (509) widths at the exit face. Divots (526) extend into a plurality of the side surfaces (322, 500B) between the slot inlets (309) and the exit face. Each individual divot (526) has a divot san depth (D55) extending into a side surface (500A, 500B, 502A, 502B) of the side surfaces (322, 500B). A ratio between a slot exit width (W53) W53 of an individual slot (324) and the divot depth (D55) of an individual divot (526) extending into a side surface (500A, 500B, 502A, 502B) of the individual slot (324) is greater than 1.2.
    Type: Application
    Filed: May 30, 2019
    Publication date: October 7, 2021
    Inventors: Thomas William Brew, Yuehao Li, Min Shen
  • Publication number: 20210305372
    Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a channel member including a first channel layer and a second channel layer over the first channel layer, and a gate structure over the channel member. The first channel layer includes silicon, germanium, a III-V semiconductor, or a II-VI semiconductor and the second channel layer includes a two-dimensional material.
    Type: Application
    Filed: July 23, 2020
    Publication date: September 30, 2021
    Inventors: Mrunal Abhijith Khaderbad, Dhanyakumar Mahaveer Sathaiya, Keng-Chu Lin, Tzer-Min Shen
  • Patent number: 11129835
    Abstract: The invention features compositions and methods for inhibiting the Pin1 protein, and the treatment of disorders characterized by elevated Pin1 levels.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: September 28, 2021
    Assignees: Beth Israel Deaconess Medical Center, Inc., The United States of America, as represented by the Secretary, Department of Health and Human Services Office of Technology Transfer, National Institutes of Health
    Inventors: Kun Ping Lu, Matthew Brian Boxer, Mindy Irene Emily Davis, Rajan Pragani, Min Shen, Anton Momtchilov Simeonov, Shuo Wei, Xiao Zhen Zhou
  • Publication number: 20210296485
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a <100> crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction.
    Type: Application
    Filed: June 7, 2021
    Publication date: September 23, 2021
    Inventors: Tzer-Min Shen, Zhiqiang Wu, Chung-Cheng Wu, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang, Min Cao
  • Publication number: 20210260535
    Abstract: The invention belongs to the technical field of composite membrane, and in particular discloses a UIO-66-NH2 doped organosilicon high salinity wastewater treatment membrane and a preparation method thereof. The membrane is formed into UIO-66-NH2/organosilicon hybrid membrane on the prefabricated ceramic support surface through the dip-coating method by doping the UIO-66-NH2 metal-organic framework material into the organosilicon polymeric sol. The UIO-66-NH2/organosilicon hybrid membrane prepared by the present invention exhibits high water permeability (up to 1.6×10?10 m3/(m2 s Pa) and high salt retention (NaCl retention rate is more than 99.9.%) in the application of pervaporation desalination, and maintains stable membrane structure in the treatment process of TDS>5 wt % high salinity wastewater.
    Type: Application
    Filed: February 3, 2021
    Publication date: August 26, 2021
    Inventors: Rong XU, Qian LIU, Chunhui ZHU, Jing ZHONG, Xiuxiu REN, Min SHEN, Yihan ZHANG
  • Patent number: 11045975
    Abstract: A honeycomb extrusion die comprising at least some slots (308) each with a divot (312) spaced toward a discharge surface (324) from a feedhole-slot intersection (332) and a wide portion at the discharge surface extending into the die body (358) to the divot (312) to strengthen a peripheral region of a honeycomb extrudate in a reinforcement region, and a bulk nominal section corresponding to a bulk region of the honeycomb body.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: June 29, 2021
    Assignee: Corning Incorporated
    Inventors: John Wilbur Allard, Thomas William Brew, Tushar Gulati, Helmut Roland Letzel, Min Shen
  • Patent number: D931052
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: September 21, 2021
    Inventor: Min Shen