Abstract: A display device includes multiple shift register groups, multiple multiplexer groups, a driver IC, and multiple pixel circuits. The driver IC is configured to control the multiple shift register groups and the multiple multiplexer groups. A shift register group of the multiple shift register groups and a multiplexer group of the multiple multiplexer groups cooperatively drive a part of pixel circuits of the multiple pixel circuits. When the shift register group and the multiplexer group are enabled in a first time period, other shift register groups and other multiplexer groups are enabled in a second time period within the first time period. The first time period is longer than the second time period to render the part of pixel circuits and another part of pixel circuits to respectively have a first frame rate and a second frame rate.

Abstract: The present embodiment of the invention provides a gate driving circuit and a display apparatus using the gate driving circuit. The gate driving circuit has a plurality of shift registers, and each shift register includes a first output unit, a first pull-down unit, a second output unit, a second pull-down unit, a voltage coupling unit, and a voltage boosting unit. The first output unit is coupled to a node and a first output end. The second output unit is coupled to the node and a second output end. The first pull-down unit is coupled to the first output end and a reference potential. The second pull-down unit is coupled to the second output end and the reference potential. The voltage coupling unit is coupled between the node and the second output end. The voltage boosting unit is coupled to a preset potential, the first output end, and a node and a gate high potential of a shift register at a previous stage.

Abstract: Power and performance of a multi-core system is managed dynamically by adjusting power table indices at runtime. Runtime statistics is measured, when an application is executed on a first core of a first type at a first operating point (OPP) in a first time period, and on a second core of a second core type at a second OPP in a second time period. A controller estimates, based on the runtime statistics, a first pair of indices associated with a first OPP for the first core and a second pair of indices associated with a second OPP for the second core. During runtime, the controller incorporates the first pair of indices and the second pair of indices into power table indices; and determines, from the power table indices, selected indices associated with a selected OPP of a core of a selected core type for executing the application.

Abstract: A display driving circuit is provided. The display driving circuit includes: at least one gate driving circuit, each of the at least one gate driving circuit generating a driving signal so that display pixels update pixel data according to each of the driving signals; and at least two enable-selecting circuits, generating a zone start-updating signal and a zone end-updating signal according to a zone scan-control signal and the driving signals and enabling the at least one gate driving circuit of a first portion according to the zone start-updating signal and the zone end-updating signal. In this way, the at least one gate driving circuit of the first portion generates the driving signals to update part of the display pixels, and that power saving is achieved.

Abstract: An end cap structure for a cane/crutch/trekking pole includes a main body, an elastic interlayer, and a bottom layer. The elastic interlayer is disposed between the main body and the bottom layer to ensure the structural strength of the end cap. When the user swings the cane/crutch/trekking pole in all directions, the whole underside of the bottom layer is kept in contact with the ground due to the elastic interlayer to ensure that the anti-slip function is not affected, thereby improving the safety of the product when in use.

Abstract: A control circuit includes a power supply switch unit and a reset switch unit. The power supply switch unit is electrically connected to a data line and a pixel circuit. When the data line has a data voltage, the power supply switch unit is turned on according to a power supply signal, so that the pixel circuit is charged by the data voltage. The reset switch unit is electrically connected to the pixel circuit. After the pixel circuit is charged by the data voltage, the reset switch unit is turned on according to the reset signal to reset a voltage of the pixel circuit to the reset voltage.

Abstract: A driving circuit includes a first driving switch, a second driving switch and a current regulating unit. The first driving switch is electrically connected to a first power source and a first light emitting element. When the first driving switch is turned on, the first driving switch is configured to receive a first current. The second driving switch is electrically connected to a second power source and a second light emitting element. When the second driving switch is turned on, the second driving switch is configured to receive a second current. The current regulating unit is electrically connected to a negative terminal of the second light emitting element and a positive terminal of the first light emitting element. When the current regulating unit is disabled, the second current sequentially flows through the second light emitting element and the first light emitting element.

Abstract: A control circuit includes a power supply switch unit and a reset switch unit. The power supply switch unit is electrically connected to a data line and a pixel circuit. When the data line has a data voltage, the power supply switch unit is turned on according to a power supply signal, so that the pixel circuit is charged by the data voltage. The reset switch unit is electrically connected to the pixel circuit. After the pixel circuit is charged by the data voltage, the reset switch unit is turned on according to the reset signal to reset a voltage of the pixel circuit to the reset voltage.

Abstract: A shift register and a touch display apparatus thereof are provided. The shift register includes a voltage setting unit, a driving unit, a control unit, a discharge unit, a first compensation transistor, and a second compensation transistor. The voltage setting unit sets a terminal voltage of an internal terminal. The driving unit is coupled to the internal terminal to provide a gate signal and a driving signal. The control unit receives the terminal voltage to provide a control signal. The discharge unit discharges the terminal voltage and the gate signal according to the control signal. The first compensation transistor and the second compensation transistor are coupled in series between a touch enable signal and the internal terminal, and control terminals of the first compensation transistor and the second compensation transistor receive the terminal voltage and the touch enable signal, respectively.

Abstract: A pixel array substrate including a substrate, a first signal line, a second signal line, a third signal line, a first active element and a conductive pattern is provided. The first signal line and the second signal line are disposed on the substrate and intersect with each other. The third signal line is disposed on the substrate and overlapped with the second signal line. The extending direction of the third signal line is parallel to the extending direction of the second signal line. The first active element is electrically connected to the first signal line. The first active element includes a semiconductor pattern, a first gate and a second gate. The semiconductor pattern is located between the first gate and the second gate. The first gate is overlapped with the second gate and connected to the third signal line. The second gate is connected to the first gate via the conductive pattern.

Abstract: A semiconductor substrate including a data line, a scan line, a capacitance control line, a first transistor, a pixel electrode, a second transistor, a storage capacitor and a third transistor is provided. A first terminal of the first transistor is electrically connected to the data line. A control terminal of the first transistor is electrically connected to the scan line. The pixel electrode is electrically connected to a second terminal of the first transistor. A first terminal of the second transistor is electrically connected to the second terminal of the first transistor. A first terminal of the third transistor is electrically connected to the capacitance control line. A control terminal of the third transistor is electrically connected to the scan line, and a second terminal of the third transistor is electrically connected to a control terminal of the second transistor.

Abstract: An active device array substrate includes: a substrate, a switch device, an inter-layer dielectric layer, an insulation bump, a conductive layer, and a pixel electrode. The switch device is located on the substrate. The inter-layer dielectric layer is located on the switch device, and the inter-layer dielectric layer has at least one opening, where the opening does not cover at least one part of a drain electrode of the switch device. The insulation bump covers at least partially the opening. The conductive layer is located on a top surface and a side wall of the insulation bump, and is electrically connected to the drain electrode of the switch device through the opening. The pixel electrode is electrically connected to the conductive layer.

Abstract: The disclosure provides a light emitting diode including a light emitting diode (LED), a first transistor, a second transistor and capacitor. A cathode terminal of the LED is configured to receive a first power supply voltage. A first port of the capacitor coupled to the gate of the first transistor is configured to store a data signal in a first duration. A first port of the second transistor is configured to receive a second power supply voltage. A gate of the second transistor is configured to receive a PWM signal in a second duration. A second port of the second transistor is coupled to the second port of the first transistor. The second transistor is turned on for a conducting time in the second duration according to the PWM signal, and the first transistor provides, in the conducting time, a drive current to the LED according to the data signal.

Abstract: A multiplexer applied to a display device includes: a plurality of switching units, electrically coupled to a data driver and a plurality of pixel units, where the switching units are adapted to receive a plurality of input display data signals output by the data driver, and the switching units output a plurality of output display data signals to the electrically coupled pixel units, where each of the switching units includes a plurality of switch units, configuration locations of the switch units in each of the switching units are the same as, and some of the switch units configured at a same configuration location in the different switching units are electrically coupled to different control signal lines and have different wiring lengths, where the wiring lengths are distances between the switch units and the control signal lines.

Abstract: An end cap structure for a cane/crutch/trekking pole includes a main body, an elastic interlayer, and a bottom layer. The elastic interlayer is disposed between the main body and the bottom layer to ensure the structural strength of the end cap. When the user swings the cane/crutch/trekking pole in all directions, the whole underside of the bottom layer is kept in contact with the ground due to the elastic interlayer to ensure that the anti-slip function is not affected, thereby improving the safety of the product when in use.

Abstract: A light-emitting device includes a substrate, a circuit array including a plurality of circuit units disposed on the substrate, a first conductive pattern, a second conductive pattern, a first wire pattern, and a second wire pattern disposed on the circuit array, and a light-emitting element disposed on one of the circuit units. The light-emitting element includes a first electrode and a second electrode respectively electrically connected to the first conductive pattern and the second conductive pattern. The second electrode is not overlapped with the first wire pattern and the second wire pattern. A manufacturing method of the light-emitting device is also provided.

Abstract: A display apparatus includes a pixel array, a plurality of gate lines and a plurality of de-load lines. The pixel array includes a plurality of display rows, each of the display rows includes a plurality of pixel circuits, and each of the pixel circuits includes a first transistor and a second transistor coupled in series between a data line and a display pixel. A control end of the first transistor of each of the pixel circuits is coupled to one of the gate lines for receiving a gate driving signal. A control end of the second transistor of each of the pixel circuits is coupled to one of the de-load lines for receiving a de-loading signal. Where an enable time period of the de-loading signal received by each of the pixel circuits covers an enable time period of the gate driving signal received by each of the pixel circuits.

Abstract: A display device includes a driving circuit and a control circuit. The driving circuit is configured to receive a data voltage in response to a scanning signal, and to control the brightness of a light emitting element according to the data voltage. The control circuit is configured to provide a stop signal to the driving circuit in response to a digital signal and the scanning signal, so as to stop the light emitting element from emitting light, and in turn control the light emission period of the light emitting element.

Abstract: A transistor device disposed on a substrate and including a semiconductor layer, a first gate, a second gate, and two source drain electrodes is provided. The semiconductor layer is disposed on the substrate and has a channel region, two lightly-doped regions, and two source drain regions. Each of the two lightly-doped regions has a first boundary adjoined to the channel region and a second boundary adjoined to one of the two source drain regions. The first gate is extended over the channel region of the semiconductor layer, wherein an edge of the first gate is aligned with the first boundary. The second gate is stacked on the first gate and is in contact with the first gate, wherein in a thickness direction, the second gate is overlapped with the two lightly-doped regions. The two source drain electrodes are respectively in contact with the two source drain regions.