Abstract: An electronic device has a processing system and a management circuit. The processing system executes an application. The management circuit detects an operating behavior of the application during execution of the application, analyzes the detected operating behavior of the application to generate an application identification result, and configures an application-dependent task according to at least the application identification result.

Abstract: Methods and apparatus are provided for adaptive thermal slope control for dynamic thermal management. In one novel aspect, the device monitors and obtains sampling temperatures, calculates a thermal-slope index, determines whether the calculated thermal-slope index is greater than a predefined slope threshold, adjusts a power budget based on a thermal-slope algorithm, and applies the dynamic thermal management (DTM) adaptively based on the adjusted power budget. In one embodiment, fixed slope algorithm is used. The power budget is adjusted such that an adjusted slope of temperatures stays at a constant. In another embodiment, the time prediction algorithm is used. The power budget is adjusted such that a predicted time to reach a predefined thermal threshold stays a constant. In one embodiment, the time-prediction algorithm is a time-to-target-point (T2TP) algorithm. The T2TP is obtained using a linear equation or a LOG equation.

Abstract: A pixel structure including scan lines, data lines, and sub-pixels is provided. The scan and data lines are disposed on the substrate. The sub-pixels include switch devices, contact pattern layer, color filter pattern layers, and pixel electrodes. The switch devices are electrically connected to one scan line and one data line respectively. The contact pattern layer and the color filter pattern layer are disposed on the substrate and the switch devices. The contact pattern layer covers part of two adjacent switch devices. At least two color filter pattern layers include a patterned opening respectively, and the contact pattern layer is disposed in the patterned opening. The pixel electrodes are disposed on the color filter pattern layer, the contact pattern layer, and the switch device. At least one pixel electrode is partially disposed between the color filter pattern layer and the corresponding switch device while electrically connected to the switch device.

Abstract: A computing system includes a multi-core processor and a core controller. The core controller is for: monitoring utilization of the multi-core processor; calculating a target performance index according to the utilization of the multi-core processor, a target utilization and a first performance index, wherein the first performance index is associated with a first entry of a dynamic voltage frequency scaling (DVFS) table that corresponds to a current setting for the multi-core processor; and selecting a second entry of the DVFS table that corresponds to a target-setting according to the target performance index and a second performance index that is associated with the second entry. The target-setting is used to configure the multi-core processor.

Abstract: A computing system with multiple processor cores manages power and performance by dynamic frequency scaling. The system detects a condition when a total number of active processor cores within one or more clusters is less than a predetermined number, and an operating frequency of the active processor cores has risen to a specified highest frequency. The system also obtains ambient temperature measurement of the one or more clusters. Upon detecting the condition, the system increases the operating frequency above the specified highest frequency based on the ambient temperature measurement while maintaining a same level of supply voltage to the active processor cores.

Abstract: A liquid crystal display panel includes a first substrate, a second substrate, at least one liquid crystal layer, a first pixel array and a second pixel array. The liquid crystal layer is interposed between the first substrate and the second substrate. The first pixel array is disposed in a first display region of the first substrate, where the first pixel array includes a plurality of first transmissive sub-pixels arranged in columns and rows and disposed adjacent to each other. The second pixel array is disposed in a second display region of the first substrate, and the second pixel array includes a plurality of reflective sub-pixels arranged in columns and rows.

Abstract: A shaft assembly (4) of a blender blade device (3) is provided. The blender blade device (3) is penetrated by the shaft assembly (4) and disposed in a blender container (1) and penetratingly disposed at the bottom of the blender container (1) to operably connect with a blender base (2). The shaft assembly (4) comprises a shaft body (41) and a wear-resistant sleeve (42). A stop ring (411) is disposed at the upper segment of the shaft body (41) and axially protrudes outward from the circumferential wall of the shaft body (41). The wear-resistant sleeve (42) axially fits around the outer wall of the shaft body (41) and has the top rim abutting against the bottom rim of the stop ring (411). The outer circumferential wall of the shaft body (41) is protected against direct contact and friction.

Abstract: A display panel includes a plurality of sub-pixels, scanning lines and data lines. The sub-pixels are disposed on a first substrate and include a plurality of rows and columns, and each sub-pixel of a first row of two adjoining rows is shifted by a predetermined distance along a first direction with respect to each sub-pixel of a second row of two adjoining rows. The scanning lines extend in the first direction and corresponding to the sub-pixels of the rows respectively. Each data line includes a plurality of first data segments and second data segments connected alternately. The first data segment extends along a second direction and partially overlaps the scanning line in a vertical direction. Each second data segment is disposed on one side of the scanning line, and at least a portion of the second data segments extends along a third direction different from the first and second directions.

Abstract: A multi-channel memory system has a memory device, a plurality of channels, and a control circuit. The memory device has a plurality of memory storage spaces. The channels are coupled to the memory storage spaces, respectively, wherein each of the channels is configured to act as a memory interface for accessing a corresponding memory storage space independently. The control circuit controls clock frequencies of clocks on the channels, respectively. At a same time point, the channels include at least a first channel operating at a first clock frequency set by the control circuit and a second channel operating at a second clock frequency set by the control circuit at a same time point, and the second clock frequency is different from the first clock frequency.

Abstract: A display panel includes a plurality of sub-pixels, scanning lines and data lines. The sub-pixels are disposed on a first substrate and include a plurality of rows and columns, and each sub-pixel of a first row of two adjoining rows is shifted by a predetermined distance along a first direction with respect to each sub-pixel of a second row of two adjoining rows. The scanning lines extend in the first direction and corresponding to the sub-pixels of the rows respectively. Each data line includes a plurality of first data segments and second data segments connected alternately. The first data segment extends along a second direction and partially overlaps the scanning line in a vertical direction. Each second data segment is disposed on one side of the scanning line, and at least a portion of the second data segments extends along a third direction different from the first and second directions.

Abstract: A discharge balancing device, for balancing a plurality of electric energy storage units connected in series in a discharge stage, comprising a plurality of bypass units, respectively connected to the plurality of electric energy storage units in parallel, configured to drain bypass currents from the plurality of electric energy storage units according to control signals; an energy condition measurement circuit, coupled to the plurality of the electric energy storage units, configured to measure energy conditions of the plurality of electric energy storage units; and a balancing control unit, coupled to the energy condition measurement circuit and the plurality of bypass units, configured to generate each of the control signals according to the energy conditions measured by the energy condition measurement circuit, so as to control each of the plurality of bypass units whether to drain a bypass current from a corresponding electric energy storage unit.

Abstract: A method and a computer-readable medium for dynamically managing power of a multi-core processor of a computing system are provided. The multi-core processor generates a dynamic voltage and frequency scaling (DVFS) table, determines a first index by alternatively selecting either a power budget or a required performance thereof, determines a current thread level parallelism (TLP) of the computing system, selects one of entries according to the current TLP and the first index, and configure first cores and second cores thereof according to a first settings and a second settings of the selected entry.

Abstract: An active device array substrate includes a flexible substrate, a gate electrode, a dielectric layer, a channel layer, a source electrode, a drain electrode, and a pixel electrode. The flexible substrate has a transistor region and a transparent region adjacent to each other. The gate electrode is disposed on the transistor region. The dielectric layer covers the flexible substrate and the gate electrode. A portion of the dielectric layer disposed on the gate electrode has a first thickness. Another portion of the dielectric layer disposed on the transparent region has a second thickness less than the first thickness. The channel layer is disposed above the gate electrode. The source electrode and the drain electrode are electrically connected to the channel layer. The pixel electrode is disposed on the dielectric layer which is disposed on the transparent region. The pixel electrode is electrically connected to the drain electrode.

Abstract: A pixel structure includes a substrate, a patterned semiconductor layer, an insulation layer, a gate electrode, a first inter-layer dielectric (ILD) layer, a second ILD layer, a third ILD layer, a source electrode and a drain electrode. The patterned semiconductor layer is disposed on the substrate. The insulation layer is disposed on the patterned semiconductor layer. The gate electrode is disposed on the insulation layer. The first ILD layer is disposed on the gate electrode, the second ILD layer is disposed on the first ILD layer, and the third ILD layer is disposed on the second ILD layer. The source electrode and the drain electrode are disposed on the third ILD layer, wherein the source electrode and the drain electrode are electrically connected to the patterned semiconductor layer via a first contact window and a second contact window respectively.

Abstract: An electronic device has a processing system and a management circuit. The processing system executes an application. The management circuit detects an operating behavior of the application during execution of the application, analyzes the detected operating behavior of the application to generate an application identification result, and configures an application-dependent task according to at least the application identification result.

Abstract: A pixel structure includes a substrate, a patterned semiconductor layer, an insulation layer, a gate electrode, a first inter-layer dielectric (ILD) layer, a second ILD layer, a third ILD layer, a source electrode and a drain electrode. The patterned semiconductor layer is disposed on the substrate. The insulation layer is disposed on the patterned semiconductor layer. The gate electrode is disposed on the insulation layer. The first ILD layer is disposed on the gate electrode, the second ILD layer is disposed on the first ILD layer, and the third ILD layer is disposed on the second ILD layer. The source electrode and the drain electrode are disposed on the third ILD layer, wherein the source electrode and the drain electrode are electrically connected to the patterned semiconductor layer via a first contact window and a second contact window respectively.

Abstract: An atomizer includes a motor mounted in a housing. First and second cylinder units are received in the housing. The first cylinder unit includes a first piston and a first coupling bearing connected to the first piston. The second cylinder unit includes a second piston and a second coupling bearing connected to the second piston. An eccentric transmission shaft of the motor extends through the first and second coupling bearings of the first and second cylinder units. The first and second pistons of the first and second cylinder units move reciprocatingly when the motor operates. An intake check valve is mounted in an intake passage between an intake port of the first cylinder unit and an inlet of the housing. An outlet check valve is mounted in an outlet passage between an outlet port of the second cylinder unit and an outlet of the housing.

Abstract: A battery condition estimating apparatus for a battery pack having a plurality of battery cells connected in series includes an analog channel switching circuit and a battery gas gauge circuit. The analog channel switching circuit has a plurality of input ports and an output port, wherein the input ports are coupled to the battery cells via a plurality of analog channels, respectively, and the analog channel switching circuit is arranged to couple the output port to a selected input port of the input ports for allowing the output port N5 to be coupled to a selected battery via a selected analog channel. The battery gas gauge circuit is coupled to the output port of the analog channel switching circuit, and used for estimating a battery condition of the battery pack by monitoring the selected battery cell via the selected analog channel.

Abstract: A method for fabricating a pixel structure includes the following steps. A patterned semiconductor layer, an insulation layer, and a patterned metal layer are formed on a substrate sequentially. A first inter-layer dielectric (ILD) layer is formed to cover the patterned metal layer. A low temperature annealing process is performed after forming the first ILD layer. A hydrogen plasma treatment process is performed after the low temperature annealing process. A second ILD layer is formed to cover the first ILD layer after the hydrogen plasma treatment process. A third ILD layer is formed to cover the second ILD layer. A source electrode and a drain electrode are formed on the third ILD layer. A passivation layer is formed on the source electrode and the drain electrode. A pixel electrode is formed on the passivation layer. A pixel structure manufactured by the above-mentioned method is also provided.

Abstract: An active device array substrate includes a flexible substrate, a gate electrode, a dielectric layer, a channel layer, a source electrode, a drain electrode, and a pixel electrode. The flexible substrate has a transistor region and a transparent region adjacent to each other. The gate electrode is disposed on the transistor region. The dielectric layer covers the flexible substrate and the gate electrode. A portion of the dielectric layer disposed on the gate electrode has a first thickness. Another portion of the dielectric layer disposed on the transparent region has a second thickness less than the first thickness. The channel layer is disposed above the gate electrode. The source electrode and the drain electrode are electrically connected to the channel layer. The pixel electrode is disposed on the dielectric layer which is disposed on the transparent region. The pixel electrode is electrically connected to the drain electrode.