Abstract: Provided is a gate driving circuit, coupled to a pixel array having multiple gate lines. The gate driving circuit includes multiple shift registers and multiple pull-up transistor, coupled to the pixel array and separately located on two opposite sides of the pixel array. Shift registers located on a same side are sequentially coupled to each other. An nth (n is a positive integer) pull-up transistor includes: a control end, coupled to a control end of a driving transistor of an (n?1)th shift register located on a same side as the nth pull-up transistor; a first end, used to receive a clock signal, where the clock signal is further input to an nth shift register of the shift registers located on an opposite side of the nth pull-up transistor; and a second end, coupled to an nth gate line of the pixel array and used to drive the nth gate line.

Abstract: A pixel structure including a first pixel unit, a second pixel unit, a first insulating layer, and a common electrode is provided. The first and second pixel units are disposed on a substrate, and includes a first drain and a first pixel electrode, and a second drain and a second pixel electrode, respectively. The first insulating layer covers the first and second drains. The first and second pixel electrodes are disposed on the first insulating layer, and the first insulating layer has first and second contact holes uncovering the first and second drains, respectively. The common electrode is disposed on the first insulating layer, and is electrically insulated from the first and second pixel electrodes, and has a common opening. When projected onto the substrate, the first and second contact holes are disposed within a region of the common opening.

Abstract: A shift register and a touch display apparatus thereof are provided. The shift register includes a voltage setting unit, a driving unit, a control unit, a discharge unit, a first compensation transistor, and a second compensation transistor. The voltage setting unit sets a terminal voltage of an internal terminal. The driving unit is coupled to the internal terminal to provide a gate signal and a driving signal. The control unit receives the terminal voltage to provide a control signal. The discharge unit discharges the terminal voltage and the gate signal according to the control signal. The first compensation transistor and the second compensation transistor are coupled in series between a touch enable signal and the internal terminal, and control terminals of the first compensation transistor and the second compensation transistor receive the terminal voltage and the touch enable signal, respectively.

Abstract: A bicycle mounting mechanism and battery box assembly installed in a bicycle frame of a bicycle is provided to include a battery box and a mounting mechanism. The battery box includes an abutment recess and an opening. The mounting mechanism includes a grip and a locating component unit being connected to the bicycle frame and defining therein an accommodation chamber for accommodating the battery box. The grip is pivotally connected to the locating component unit and includes an abutment end portion and a push end portion. The abutment end portion is capable of inserting into the accommodation chamber and in engagement with the opening with a rotating of the grip. The push end portion is capable of inserting into the accommodation chamber and abuts against the abutment recess with a further rotating of the grip.

Abstract: A multiplexer applied to a display device includes: a plurality of switching units, electrically coupled to a data driver and a plurality of pixel units, where the switching units are adapted to receive a plurality of input display data signals output by the data driver, and the switching units output a plurality of output display data signals to the electrically coupled pixel units, where each of the switching units includes a plurality of switch units, configuration locations of the switch units in each of the switching units are the same as, and some of the switch units configured at a same configuration location in the different switching units are electrically coupled to different control signal lines and have different wiring lengths, where the wiring lengths are distances between the switch units and the control signal lines.

Abstract: Provided is a gate driving circuit, coupled to a pixel array having multiple gate lines. The gate driving circuit includes multiple shift registers and multiple pull-up transistor, coupled to the pixel array and separately located on two opposite sides of the pixel array. Shift registers located on a same side are sequentially coupled to each other. An nth (n is a positive integer) pull-up transistor includes: a control end, coupled to a control end of a driving transistor of an (n?1)th shift register located on a same side as the nth pull-up transistor; a first end, used to receive a clock signal, where the clock signal is further input to an nth shift register of the shift registers located on an opposite side of the nth pull-up transistor; and a second end, coupled to an nth gate line of the pixel array and used to drive the nth gate line.

Abstract: An anti-interference display panel includes a source driving chip, a switching signal line, a multiplexer, and an anti-interference signal line. The source driving chip is configured to generate a data signal. The switching signal line is configured to transmit a switching signal. The multiplexer is configured to receive the data signal and the switching signal, and is configured to output the data signal according to the switching signal. The anti-interference signal line is configured to transmit an anti-interference signal. An equivalent resistor and an equivalent capacitor are formed on the anti-interference signal line, and resistance of the equivalent resistor is approximate to resistance of a load resistor coupled to the switching signal line, and capacitance of the equivalent capacitor is approximate to capacitance of a load capacitor coupled to the switching signal line.

Abstract: The present embodiment of the invention provides a gate driving circuit and a display apparatus using the gate driving circuit. The gate driving circuit has a plurality of shift registers, and each shift register includes a first output unit, a first pull-down unit, a second output unit, a second pull-down unit, a voltage coupling unit, and a voltage boosting unit. The first output unit is coupled to a node and a first output end. The second output unit is coupled to the node and a second output end. The first pull-down unit is coupled to the first output end and a reference potential. The second pull-down unit is coupled to the second output end and the reference potential. The voltage coupling unit is coupled between the node and the second output end. The voltage boosting unit is coupled to a preset potential, the first output end, and a node and a gate high potential of a shift register at a previous stage.

Abstract: An active device array substrate includes: a substrate, a switch device, an inter-layer dielectric layer, an insulation bump, a conductive layer, and a pixel electrode. The switch device is located on the substrate. The inter-layer dielectric layer is located on the switch device, and the inter-layer dielectric layer has at least one opening, where the opening does not cover at least one part of a drain electrode of the switch device. The insulation bump covers at least partially the opening. The conductive layer is located on a top surface and a side wall of the insulation bump, and is electrically connected to the drain electrode of the switch device through the opening. The pixel electrode is electrically connected to the conductive layer.

Abstract: A computing system includes a multi-core processor and a core controller. The core controller is for: monitoring utilization of the multi-core processor; calculating a target performance index according to the utilization of the multi-core processor, a target utilization and a first performance index, wherein the first performance index is associated with a first entry of a dynamic voltage frequency scaling (DVFS) table that corresponds to a current setting for the multi-core processor; and selecting a second entry of the DVFS table that corresponds to a target-setting according to the target performance index and a second performance index that is associated with the second entry. The target-setting is used to configure the multi-core processor.

Abstract: A pixel structure is disposed on a substrate and includes a bump, a first insulating layer, a semiconductive layer, a second insulating layer, a metal layer, and a pixel electrode. The bump is disposed on the substrate. The first insulating layer is disposed on the substrate and covers the bump. The first insulating layer has a protruding portion at the position at which the first insulating layer covers the bump. The semiconductive layer is disposed on the first insulating layer, and at least a portion of the semiconductive layer is disposed above the protruding portion. The second insulating layer is disposed on the first insulating layer and covers the semiconductive layer. The second insulating layer has a via, so as to make a portion of the semiconductive layer be not covered by the second insulating layer. The via corresponds to the protruding portion in a direction perpendicular to the substrate. The metal layer is electrically connected to the semiconductive layer through the via.

Abstract: A pixel structure including scan lines, data lines, and sub-pixels is provided. The scan and data lines are disposed on the substrate. The sub-pixels include switch devices, contact pattern layer, color filter pattern layers, and pixel electrodes. The switch devices are electrically connected to one scan line and one data line respectively. The contact pattern layer and the color filter pattern layer are disposed on the substrate and the switch devices. The contact pattern layer covers part of two adjacent switch devices. At least two color filter pattern layers include a patterned opening respectively, and the contact pattern layer is disposed in the patterned opening. The pixel electrodes are disposed on the color filter pattern layer, the contact pattern layer, and the switch device. At least one pixel electrode is partially disposed between the color filter pattern layer and the corresponding switch device while electrically connected to the switch device.

Abstract: A wafer container is provided. The wafer container includes a pod base having a top surface and a bottom surface, a cassette disposed on the top surface, and a damping device, disposed on the bottom surface. The damping device includes a housing disposed in the pod base, and a damping mechanism disposed in the housing and protruding over the bottom surface. The damping mechanism is configured to provide a damping force.

Abstract: A controller coupled to a plurality of hardware modules is arranged for determining activities of at least two of the hardware modules in real time, and determining a voltage and a frequency for one of the hardware modules according to the activities of the at least two of the hardware modules.

Abstract: A wafer container is provided. The wafer container includes a pod base having a top surface and a bottom surface, a cassette disposed on the top surface, and a damping device, disposed on the bottom surface. The damping device includes a housing disposed in the pod base, and a damping mechanism disposed in the housing and protruding over the bottom surface. The damping mechanism is configured to provide a damping force.

Abstract: An atomizer includes a motor mounted in a housing. First and second cylinder units are received in the housing. The first cylinder unit includes a first piston and a first coupling bearing connected to the first piston. The second cylinder unit includes a second piston and a second coupling bearing connected to the second piston. An eccentric transmission shaft of the motor extends through the first and second coupling bearings of the first and second cylinder units. The first and second pistons of the first and second cylinder units move reciprocatingly when the motor operates. An intake check valve is mounted in an intake passage between an intake port of the first cylinder unit and an inlet of the housing. An outlet check valve is mounted in an outlet passage between an outlet port of the second cylinder unit and an outlet of the housing.

Abstract: A discharge balancing device, for balancing a plurality of electric energy storage units connected in series in a discharge stage, comprising a plurality of bypass units, respectively connected to the plurality of electric energy storage units in parallel, configured to drain bypass currents from the plurality of electric energy storage units according to control signals; an energy condition measurement circuit, coupled to the plurality of the electric energy storage units, configured to measure energy conditions of the plurality of electric energy storage units; and a balancing control unit, coupled to the energy condition measurement circuit and the plurality of bypass units, configured to generate each of the control signals according to the energy conditions measured by the energy condition measurement circuit, so as to control each of the plurality of bypass units whether to drain a bypass current from a corresponding electric energy storage unit.

Abstract: A pixel structure including a first pixel unit, a second pixel unit, a first insulating layer, and a common electrode is provided. The first and second pixel units are disposed on a substrate, and includes a first drain and a first pixel electrode, and a second drain and a second pixel electrode, respectively. The first insulating layer covers the first and second drains. The first and second pixel electrodes are disposed on the first insulating layer, and the first insulating layer has first and second contact holes uncovering the first and second drains, respectively. The common electrode is disposed on the first insulating layer, and is electrically insulated from the first and second pixel electrodes, and has a common opening. When projected onto the substrate, the first and second contact holes are disposed within a region of the common opening.

Abstract: A multi-channel memory system has a memory device, a plurality of channels, and a control circuit. The memory device has a plurality of memory storage spaces. The channels are coupled to the memory storage spaces, respectively, wherein each of the channels is configured to act as a memory interface for accessing a corresponding memory storage space independently. The control circuit controls clock frequencies of clocks on the channels, respectively. At a same time point, the channels include at least a first channel operating at a first clock frequency set by the control circuit and a second channel operating at a second clock frequency set by the control circuit at a same time point, and the second clock frequency is different from the first clock frequency.