Patents by Inventor Ming Mao

Ming Mao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11935753
    Abstract: A method for forming a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices, each integrated circuit device extending into the semiconductor wafer to a first depth, and grinding a backside of the silicon wafer to no more than the first depth. The method further includes forming a backside cut between the integrated circuit devices. The backside cut extends to within the first depth, but the backside cut does not extend completely through the semiconductor wafer. The backside cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on the backside of the wafer, a metallization layer on a bottom surface of the integrated circuit devices and on the edges.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: March 19, 2024
    Assignee: NXP B.V
    Inventors: Kuan-Hsiang Mao, Wen Hung Huang, Che Ming Fang, Yufu Liu
  • Patent number: 11929385
    Abstract: A method for forming a pixelated optoelectronic stack comprises forming a stacked layer structure that comprises a bottom electrode layer, an optoelectronic layer over the bottom electrode layer, and a patterned hard-mask comprising a pattern over the optoelectronic layer. The method comprises replicating the pattern into the optoelectronic layer and the bottom electrode layer, thereby forming a first intermediate pixelated stack comprising at least two islands of stack separated from one another by stack-free areas; providing an electrically insulating layer on the first intermediate pixelated stack; removing a top portion of the electrically insulating layer and removing any remaining hard-mask so that a top surface of the electrically insulating layer is coplanar with an exposed top surface of the first intermediate pixelated stack, yielding a second intermediate pixelated stack; and forming a top transparent electrode layer over the second intermediate pixelated stack.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: March 12, 2024
    Assignee: Imec vzw
    Inventors: Yunlong Li, Stefano Guerrieri, Ming Mao, Luis Moreno Hagelsieb
  • Publication number: 20240071413
    Abstract: The present disclosure generally relates to a dual free layer (DFL) read head and methods of forming thereof. In one embodiment, a method of forming a DFL read head comprises depositing a DFL sensor, defining a stripe height of the DFL sensor, depositing a rear bias (RB) adjacent to the DFL sensor, defining a track width of the DFL sensor and the RB, and depositing synthetic antiferromagnetic (SAF) soft bias (SB) side shields adjacent to the DFL sensor. In another embodiment, a method of forming a DFL read head comprises depositing a DFL sensor, defining a track width of the DFL sensor, depositing SAF SB side shields adjacent to the DFL sensor, defining a stripe height of the DFL sensor and the SAF SB side shield, depositing a RB adjacent to the DFL sensor and the SAF SB side shield, and defining a track width of the RB.
    Type: Application
    Filed: August 31, 2022
    Publication date: February 29, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Ming MAO, Yung-Hung WANG, Chih-Ching HU, Chen-Jung CHIEN, Carlos CORONA, Hongping YUAN, Ming JIANG, Goncalo Marcos BAIÃO DE ALBUQUERQUE
  • Patent number: 11778853
    Abstract: A display panel and manufacturing methods thereof are provided. In one example, the display panel includes a flexible substrate having a display area and a non-display area, a dam structure located in the non-display area and disposed around the display area, one or more grooves disposed on the non-display area between the display area and the dam structure, and an organic encapsulation layer. In some examples, the organic encapsulation layer covers each of the display area, at least a portion of the non-display area, and the one or more grooves. Accordingly, a display device comprising the display panel is also provided. Thus, a flatness of the organic encapsulation layer may be improved and peeling may be reduced between the organic encapsulation layer and a substrate on which the organic encapsulation layer is disposed, thereby improving an overall quality of the finished display panel.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: October 3, 2023
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ying Liu, Ming Mao, Yuhang Peng
  • Patent number: 11598828
    Abstract: The present disclosure generally relates to a Wheatstone bridge array that has four resistors. Each resistor includes a plurality of TMR structures. Two resistors have identical TMR structures. The remaining two resistors also have identical TMR structures, though the TMR structures are different from the other two resistors. Additionally, the two resistors that have identical TMR structures have a different resistance area as compared to the remaining two resistors that have identical TMR structures. Therefore, the working bias field for the Wheatstone bridge array is non-zero.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: March 7, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yuankai Zheng, Christian Kaiser, Zhitao Diao, Chih-Ching Hu, Chen-jung Chien, Yung-Hung Wang, Dujiang Wan, Ronghui Zhou, Ming Mao, Ming Jiang, Daniele Mauri
  • Patent number: 11569332
    Abstract: A display substrate and a display device are provided in the present invention. The display substrate includes a base substrate, and a positive power supply line, a negative power supply line and a first dam which are on the base substrate. The base substrate includes a display region and a peripheral region arranged around the display region. The positive power supply line, the negative power supply line and the first dam are in the peripheral region, and the first dam is arranged around the display region. At least in a corresponding region between the positive power supply line and the negative power supply line, a protruding structure is on a side of the first dam proximal to the display region.
    Type: Grant
    Filed: December 25, 2019
    Date of Patent: January 31, 2023
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ming Mao, Pan Zhao, Li Song, Ge Wang, Zhiliang Jiang
  • Patent number: 11532324
    Abstract: The present disclosure generally relates to a read head assembly having a dual free layer (DFL) structure disposed between a first shield and a second shield at a media facing surface. The read head assembly further comprises a rear hard bias (RHB) structure disposed adjacent to the DFL structure recessed from the media facing surface, where an insulation layer separates the RHB structure from the DFL structure. The insulation layer is disposed perpendicularly between the first shield and the second shield. The DFL structure comprises a first free layer and a second free layer having equal stripe heights from the media facing surface to the insulation layer. The RHB structure comprises a seed layer, a bulk layer, and a capping layer. The capping layer and the insulation layer prevent the bulk layer from contacting the second shield.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: December 20, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ming Mao, Chen-Jung Chien, Daniele Mauri, Goncalo Marcos Baião De Albuquerque
  • Patent number: 11514934
    Abstract: The present disclosure generally relates to a dual free layer (DFL) two dimensional magnetic recording (TDMR) read head. The read head comprises a first sensor, a first rear hard bias (RHB) structure disposed adjacent to the first sensor, an upper shield disposed over the first sensor and first RHB structure, a lower shield disposed over the upper shield, a second sensor disposed over the lower shield, and a second RHB structure disposed adjacent to the second sensor. A first surface of the first sensor is substantially flush or aligned with a first surface of the first RHB structure. A first surface of the second sensor is substantially flush or aligned with a first surface of the second RHB structure. The upper shield extends linearly from a media facing surface into the read head. The first lower shield is over-milled a greater amount of time than the second lower shield.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: November 29, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ming Mao, Chen-Jung Chien, Daniele Mauri, Goncalo Marcos Baião De Albuquerque, Chih-Ching Hu, Anup Ghosh Roy, Yung-Hung Wang
  • Patent number: 11514933
    Abstract: The present disclosure generally relates to read heads having dual free layer (DFL) sensors. The read head has a sensor disposed between two shields. The sensor is a DFL sensor and has a surface at the media facing surface (MFS). Recessed from the DFL sensor, and from the MFS, is a rear hard bias (RHB) structure. The RHB structure is disposed between the shields as well. In between the DFL sensor and the RHB structure is insulating material. The RHB is disposed on the insulating material. The RHB includes a RHB seed layer as well as a RHB bulk layer. The RHB bulk layer includes a first bulk layer and a second bulk layer, the first bulk layer having a different density relative to the second bulk layer.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: November 29, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Chen-Jung Chien, Ming Mao, Daniele Mauri
  • Patent number: 11493573
    Abstract: A tunneling magnetoresistance (TMR) sensor device is disclosed that includes four or more TMR resistors. The TMR sensor device comprises a first TMR resistor comprising a first TMR film, a second TMR resistor comprising a second TMR film different than the first TMR film, a third TMR resistor comprising the second TMR film, and a fourth TMR resistor comprising the first TMR film. The first, second, third, and fourth TMR resistors are disposed in the same plane. The first TMR film comprises a synthetic anti-ferromagnetic pinned layer having a magnetization direction of the reference layer orthogonal to a free layer. The second TMR film comprises a double synthetic anti-ferromagnetic pinned layer having a magnetization direction of the reference layer orthogonal to the magnetization of a free layer, but opposite to the magnetization direction of the reference layer of the first TMR film.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: November 8, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Chih-Ching Hu, Yung-Hung Wang, Ann Lorraine Carvajal, Ming Mao, Chen-Jung Chien, Yuankai Zheng, Ronghui Zhou, Dujiang Wan, Carlos Corona, Daniele Mauri, Ming Jiang
  • Patent number: 11495252
    Abstract: The present disclosure generally relates to a Wheatstone bridge array that has four resistors. Each resistor includes a plurality of TMR films. Each resistor has identical TMR films. The TMR films of two resistors have reference layers that have an antiparallel magnetic orientation relative to the TMR films of the other two resistors. To ensure the antiparallel magnetic orientation, the TMR films are all formed simultaneously and annealed in a magnetic field simultaneously. Thereafter, the TMR films of two resistors are annealed a second time in a magnetic field while the TMR films of the other two resistors are not annealed a second time.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: November 8, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yuankai Zheng, Ming Mao, Daniele Mauri, Chih-Ching Hu, Chen-Jung Chien
  • Patent number: 11428758
    Abstract: A tunneling magnetoresistance (TMR) sensor device is disclosed that includes one or more TMR resistors. The TMR sensor device comprises a first TMR resistor comprising a first TMR film, a second TMR resistor comprising a second TMR film different than the first TMR film, a third TMR resistor comprising the second TMR film, and a fourth TMR resistor comprising the first TMR film. The first and fourth TMR resistors are disposed in a first plane while the second and third TMR resistors are disposed in a second plane different than the first plane. The first TMR film comprises a synthetic anti-ferromagnetic pinned layer having a magnetization direction of a reference layer orthogonal to a magnetization direction a free layer. The second TMR film comprises a double synthetic anti-ferromagnetic pinned layer having a magnetization direction of a reference layer orthogonal to a magnetization direction of a free layer.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: August 30, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Chih-Ching Hu, Yung-Hung Wang, Ming Mao, Daniele Mauri, Ming Jiang
  • Patent number: 11415645
    Abstract: The present disclosure generally relates to a Wheatstone bridge array comprising TMR sensors and a method of fabrication thereof. In the Wheatstone bridge array, there are four distinct TMR sensors. The TMR sensors are all fabricated simultaneously to create four identical TMR sensors that have synthetic antiferromagnetic free layers as the top layer. The synthetic antiferromagnetic free layers comprise a first magnetic layer, a spacer layer, and a second magnetic layer. After forming the four identical TMR sensors, the spacer layer and the second magnetic layer are removed from two TMR sensors. Following the removal of the spacer layer and the second magnetic layer, a new magnetic layer is formed on the now exposed first magnetic layer such that the new magnetic layer has substantially the same thickness as the spacer layer and second magnetic layer combined.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: August 16, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yuankai Zheng, Christian Kaiser, Zhitao Diao, Chih-Ching Hu, Chen-jung Chien, Yung-Hung Wang, Ming Mao, Ming Jiang
  • Patent number: 11410690
    Abstract: The present disclosure generally related to a two dimensional magnetic recording (TDMR) read head having a magnetic tunnel junction (MTJ). Both the upper reader and the lower reader have a dual free layer (DFL) MTJ structure between two shields. A synthetic antiferromagnetic (SAF) soft bias structure bounds the MTJ, and a rear hard bias (RHB) structure is disposed behind the MTJ. The DFL MTJ decreases the distance between the upper and lower reader and hence, improves the area density capacity (ADC). Additionally, the SAF soft bias structures and the rear head bias structure cause the dual free layer MTJ to have a scissor state magnetic moment at the media facing surface (MFS).
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: August 9, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Chih-Ching Hu, Yung-Hung Wang, Ming Mao, Guanxiong Li, Daniele Mauri, Xiaoyong Liu, Yukimasa Okada, Anup Roy, Chen-Jung Chien, Hongxue Liu
  • Publication number: 20220246885
    Abstract: A display panel and manufacturing methods thereof are provided. In one example, the display panel includes a flexible substrate having a display area and a non-display area, a dam structure located in the non-display area and disposed around the display area, one or more grooves disposed on the non-display area between the display area and the dam structure, and an organic encapsulation layer. In some examples, the organic encapsulation layer covers each of the display area, at least a portion of the non-display area, and the one or more grooves. Accordingly, a display device comprising the display panel is also provided. Thus, a flatness of the organic encapsulation layer may be improved and peeling may be reduced between the organic encapsulation layer and a substrate on which the organic encapsulation layer is disposed, thereby improving an overall quality of the finished display panel.
    Type: Application
    Filed: April 21, 2022
    Publication date: August 4, 2022
    Inventors: Ying LIU, Ming MAO, Yuhang PENG
  • Patent number: 11385306
    Abstract: Embodiments of the present disclosure generally relate to a sensor of magnetic tunnel junctions (MTJs) with shape anisotropy. In one embodiment, a tunnel magnetoresistive (TMR) based magnetic sensor in a Wheatstone configuration includes at least one magnetic tunnel junctions (MTJ). The MTJ includes a free layer having a first edge and a second edge. The free layer has a thickness of about 100 ? or more. The free layer has a width and a height with a width-to-height aspect ratio of about 4:1 or more. The MTJ has a first hard bias element positioned proximate the first edge of the free layer and a second hard bias element positioned proximate the second edge of the free layer.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: July 12, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Daniele Mauri, Lei Wang, Yuankai Zheng, Christian Kaiser, Chih-Ching Hu, Ming Mao, Ming Jiang, Petrus Antonius Van Der Heijden
  • Patent number: 11385305
    Abstract: A tunneling magnetoresistance (TMR) sensor device is disclosed that includes one or more TMR sensors. The TMR sensor device comprises a first resistor comprising a first TMR film, a second resistor comprising a second TMR film different than the first TMR film, a third resistor comprising the second TMR film, and a fourth resistor comprising the first TMR film. The first TMR film comprises a reference layer having a first magnetization direction anti-parallel to a second magnetization direction of a pinned layer. The second TMR film comprises a reference layer having a first magnetization direction parallel to a second magnetization direction of a first pinned layer, and a second pinned layer having a third magnetization direction anti-parallel to the first magnetization direction of the reference layer and the second magnetization direction of the first pinned layer.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: July 12, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Yuankai Zheng, Christian Kaiser, Zhitao Diao, Chih-Ching Hu, Chen-Jung Chien, Yung-Hung Wang, Dujiang Wan, Ronghui Zhou, Ming Mao, Ming Jiang, Daniele Mauri
  • Patent number: 11342532
    Abstract: A display panel and manufacturing methods thereof are provided. In one example, the display panel includes a flexible substrate having a display area and a non-display area, a dam structure located in the non-display area and disposed around the display area, one or more grooves disposed on the non-display area between the display area and the dam structure, and an organic encapsulation layer. In some examples, the organic encapsulation layer covers each of the display area, at least a portion of the non-display area, and the one or more grooves. Accordingly, a display device comprising the display panel is also provided. Thus, a flatness of the organic encapsulation layer may be improved and peeling may be reduced between the organic encapsulation layer and a substrate on which the organic encapsulation layer is disposed, thereby improving an overall quality of the finished display panel.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: May 24, 2022
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO.. LTD.
    Inventors: Ying Liu, Ming Mao, Yuhang Peng
  • Publication number: 20220115035
    Abstract: The present disclosure generally relates to a read head assembly having a dual free layer (DFL) structure disposed between a first shield and a second shield at a media facing surface. The read head assembly further comprises a rear hard bias (RHB) structure disposed adjacent to the DFL structure recessed from the media facing surface, where an insulation layer separates the RHB structure from the DFL structure. The insulation layer is disposed perpendicularly between the first shield and the second shield. The DFL structure comprises a first free layer and a second free layer having equal stripe heights from the media facing surface to the insulation layer. The RHB structure comprises a seed layer, a bulk layer, and a capping layer. The capping layer and the insulation layer prevent the bulk layer from contacting the second shield.
    Type: Application
    Filed: February 24, 2021
    Publication date: April 14, 2022
    Inventors: Ming MAO, Chen-Jung CHIEN, Daniele MAURI, Goncalo Marcos BAIÃO DE ALBUQUERQUE
  • Patent number: 11259069
    Abstract: A system for providing video playback comprises a processor configured to synchronize clocks on the plurality of devices to a standard time, provide target video playback positions to the plurality of devices, wherein target video playback positions are based at least in part on the timing information, provide one or more locators for video streams to the plurality of devices, monitor playback status for each of the plurality of devices, and for a device, determine whether the playback status for the device indicates that a selected bitrate is too low or too high or that the playback is fast or slow; in response to determining the selected bitrate is too low, indicate to select a higher bitrate for a device; and in response to determining the selected bitrate is too high, indicate to select a lower bitrate for the device.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: February 22, 2022
    Assignee: VisualOn, Inc.
    Inventors: Cheng-Ta Hsieh, Hyoheon Hong, Huan-Chih Tsai, Ming-Mao Chiang, Yubao Li