Abstract: A method for programming a non-volatile memory structure, comprises initiating a two-dimensional fractional number of bits-per-cell programming scheme of a plurality of memory cells, wherein the memory structure comprises: (1) a first memory array comprising a first population of memory cells and the associated peripheral circuitry disposed below the first population of cells, (2) a second memory array positioned above the first memory array and comprising a second population of memory cells and associated peripheral circuitry disposed above the second population of cells, and (3) a data bus tap electrically coupling the first and second memory arrays. Further, the method comprises: (1) storing input data in data latches associated with the first array and with the second array. Additionally, the method comprises converting the stored data using data conversion logic implemented by a data path circuit of the first and second arrays and rewriting the converted data to the latches.

Abstract: A method for programming a non-volatile memory structure, comprises initiating a two-dimensional fractional number of bits-per-cell programming scheme of a plurality of memory cells, wherein the memory structure comprises: (1) a first memory array comprising a first population of memory cells and the associated peripheral circuitry disposed below the first population of cells, (2) a second memory array positioned above the first memory array and comprising a second population of memory cells and associated peripheral circuitry disposed above the second population of cells, and (3) a data bus tap electrically coupling the first and second memory arrays. Further, the method comprises: (1) storing input data in data latches associated with the first array and with the second array. Additionally, the method comprises converting the stored data using data conversion logic implemented by a data path circuit of the first and second arrays and rewriting the converted data to the latches.

Abstract: A method for programming a non-volatile memory structure, wherein the method comprises initiating a two-dimensional fractional number of bits-per-cell programming scheme with respect to at least a first memory cell and a second memory cell of a plurality of memory cells of the memory structure, wherein the memory structure comprises: (1) a first memory array that comprises a first population of the plurality of memory cells and associated peripheral circuitry disposed below the first population of the plurality of memory cells, (2) a second memory array that is positioned above the first memory array and comprises a second population of the plurality of memory cells and the associated peripheral circuitry that is disposed above the second population of the plurality of memory cells, and (3) a data bus tap electrically coupling the first memory array and the second memory array.

Abstract: A lubricating oil composition which can reduce the occurrence frequency of LSPI and which can ensure detergency. The lubricating oil composition which includes a lubricant base oil, a compound having calcium and/or magnesium, a compound having molybdenum and/or phosphorus, and an ashless dispersant having nitrogen and which satisfies X??0.85 and Y?0.18 (wherein X is calculated according to formula (1): X=([Ca]+0.5[Mg])×8?[Mo]×8?[P]×30 and Y is calculated according to formula (2): Y=[Ca]+1.65[Mg]+[N]). The lubricating oil composition for use in an internal combustion engine, more particularly, a lubricating oil composition for use in a supercharged gasoline engine.

Abstract: A static timing analysis controller includes a feedback loop identification module that identifies invariable flip flop feedback loops of an integrated circuit design, and adds the identified feedback loops to false path lists. The static timing analysis controller then performs timing update operations and identifies hold violations based on the invariable flip flop feedback loops included in the false path list. In turn, the static timing analysis controller identifies reduced or less pessimistic numbers of hold violations, resulting in fewer buffers added to the integrated circuit design.

Abstract: A static timing analysis controller includes a feedback loop identification module that identifies invariable flip flop feedback loops of an integrated circuit design, and adds the identified feedback loops to false path lists. The static timing analysis controller then performs timing update operations and identifies hold violations based on the invariable flip flop feedback loops included in the false path list. In turn, the static timing analysis controller identifies reduced or less pessimistic numbers of hold violations, resulting in fewer buffers added to the integrated circuit design.

Abstract: A lubricating oil composition which can reduce the occurrence frequency of LSPI and which can ensure detergency. The lubricating oil composition which includes a lubricant base oil, a compound having calcium and/or magnesium, a compound having molybdenum and/or phosphorus, and an ashless dispersant having nitrogen and which satisfies X??0.85 and Y?0.18 (wherein X is calculated according to formula (1): X=([Ca]+0.5[Mg])×8?[Mo]×8?[P]×30 and Y is calculated according to formula (2): Y=[Ca]+1.65[Mg]+[N]). The lubricating oil composition for use in an internal combustion engine, more particularly, a lubricating oil composition for use in a supercharged gasoline engine.

Abstract: Provided is a resin film that can be firmly adhered to fabric materials formed of chemical/synthetic fibers and natural fibers such as Japanese paper, nonwoven fabrics, textiles, and tatami-matting, and that has extremely low moisture permeability and oxygen permeability for enabling the fabric material to be suitable as excellent automobile interior materials, railroad vehicle interior materials, members for housings, and household appliance members. More specifically, the present invention is a resin film (10) including: a melt-adhesion filling layer (12) formed of an olefin based resin that contains a modified polyolefin resin and has a melt flow rate (MFR: test condition being 170° C. under a load of 2.16 kg) higher than 0.5 g/10 min but lower than 54.0 g/10 min; and a functional layer (14) formed of a thermoplastic resin and laminated on a surface of the melt-adhesion filling layer (12).

Abstract: This invention provides a coolant composition for an internal combustion engine that can improve the energy efficiency of an internal combustion engine and a method for operating an internal combustion engine using such coolant composition. The coolant composition for an internal combustion engine of the invention has kinematic viscosity of 8.5 to 3,000 mm2/sec at 25° C. and 0.3 to 1.3 mm2/sec at 100° C. The method for operating an internal combustion engine of the invention is carried out with the use of such composition.

Abstract: Provided is a resin film that can be firmly adhered to a native wood sliced veneer, has extremely low moisture permeability and oxygen permeability, and can provide the sliced veneer with excellent automobile interior suitability. A resin film 10 of the present invention includes: a melt-adhesion filling layer 12 formed of an olefin based resin whose melt flow rate (MFR: test condition being 170° C. and 2.1 kgf) is 2.5 to 33.0 g/10 min, the olefin based resin including a modified polyolefin resin; and a functional layer 14 that is formed of a thermoplastic resin and that is to be laminated on a surface of the melt-adhesion filling layer 12.

Abstract: [Problem] To provide a lubricating oil composition capable of attaining high-level fuel efficiency, durability and piston detergency in internal-combustion engines. [Means for Resolution] The lubricating oil composition according to the present invention contains a viscosity index improver and a metallic detergent in at least one base oil selected from mineral oils and synthetic oils therein, wherein the viscosity index improver contains a polymethacrylate viscosity index improver and an olefin copolymer viscosity index improver, the polymethacrylate viscosity index improver is contained in an amount of from 3.0% by mass to 9.5% by mass based on the total amount of the lubricating oil composition, the metallic detergent is at least one selected from calcium sulfonate, calcium phenate and calcium salicylate, the calcium amount derived from the metallic detergent is from 500 ppm to 1500 ppm based on the total amount of the lubricating oil composition, the high-temperature high-shear viscosity at 150° C.

Abstract: This invention provides a coolant composition for an internal combustion engine that can improve the energy efficiency of an internal combustion engine and a method for operating an internal combustion engine using such coolant composition. The coolant composition for an internal combustion engine of the invention has kinematic viscosity of 8.5 to 3,000 mm2/sec at 25° C. and 0.3 to 1.3 mm2/sec at 100° C. The method for operating an internal combustion engine of the invention is carried out with the use of such composition.

Abstract: A lubricating oil composition for a continuously variable transmission has low viscosity to exhibit fuel savings, higher metal-to-metal friction coefficient to ensure high power transmission, wet clutch friction characteristics and anti-shudder properties required for transmissions, and low traction coefficient to achieve fuel savings. The composition contains a base oil adjusted so the product (EC×V40) of the mass % (ECmass %) of saturated cyclic component based on the total base oil and the 40° C. kinematic viscosity (V40 mm2/s) is 500 or less and the 100° C. kinematic viscosity is 3.6 to 4.1 mm2/s, (B) a phosphorus compound, (C) a calcium salicylate and/or a calcium sulfonate, (D) a boron-modified ashless dispersant in an amount of 0.001 to 0.008 mass % as boron, and (E) a friction modifier, each in a specific amount, the lubricating oil composition having a 100° C. kinematic viscosity of 5.2 to 5.6 mm2/s and a viscosity index of 165 or greater.

Abstract: A semiconductor device in accordance with one embodiment of the invention can include a first data storage region including a non-volatile main data storage region. Additionally, the semiconductor device can include a second data storage region including a non-volatile reference region wherein an erasing operation and a writing operation are performed on both the first data storage region and the second data storage region. Moreover, the semiconductor device can also include a control unit coupled to the first and second data storage regions which determines a stress condition corresponding to the first data storage region based on a stress information related to the second data storage region.

Abstract: A nonvolatile memory device that responds to a decrease in electric charge stored in memory cells attributed to the charge loss phenomenon occurring during program operation by adjusting the level of a program verify operation according to the degree of the charge loss so that the program operation can be performed with little (if any) interruption.

Abstract: A semiconductor device in accordance with one embodiment of the invention can include a first data storage region including a non-volatile main data storage region. Additionally, the semiconductor device can include a second data storage region including a non-volatile reference region wherein an erasing operation and a writing operation are performed on both the first data storage region and the second data storage region. Moreover, the semiconductor device can also include a control unit coupled to the first and second data storage regions which determines a stress condition corresponding to the first data storage region based on a stress information related to the second data storage region.

Abstract: A nonvolatile memory device that responds to a decrease in electric charge stored in memory cells attributed to the charge loss phenomenon occurring during program operation by adjusting the level of a program verify operation according to the degree of the charge loss so that the program operation can be performed with little (if any) interruption.

Abstract: According to an aspect of the invention, there is provided an information processing apparatus including: a display unit configured to display a plurality of informations having a plurality of hierarchies; a focus control unit configured to focus at least one of the plurality of informations to be displayed by the display unit; a recognition unit configured to recognize whether or not a focus movement speed in at least one of the plurality of informations controlled by the focus control unit is smaller than a prescribed reference value; and a first control unit configured to control the display unit to display at least one of the plurality of informations according to the recognition result by the recognition unit.

Abstract: According to an aspect of the invention, there is provided an information processing device including: a display unit configured to display a plurality of setting informations of a setting of function indicated by indication information displayed on a standby screen; a key unit configured to accept a selection of one piece of setting information among the plurality of setting informations; a control unit configured to cancel or change function setting, based on the setting information of which the selection is accepted by the key unit; and a display control unit configured to control a display of the indication information, which is performed by the display unit, in accordance with the cancel or the change of function setting performed by the control unit.

Abstract: The semiconductor device includes a memory cell array that includes memory cells for storing data and is managed on a sector basis, a memory that stores the information determining the activation status, a latch circuit that latches the activation information according to the information stored in the memory, and a circuit that latches the activation information according to the information stored in the memory in the latch circuit. The activation information according to the memory state of the memory is latched at the time of inputting a given command after activation, and it is thus possible to read the information stored in the memory and set the information in the latch circuit certainly.