Patents by Inventor Minoru Yamashita

Minoru Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7224602
    Abstract: A semiconductor device includes a first memory cell array that includes memory cells for storing data and is managed on a sector basis, a second memory cell array including memory cells storing sector protection information on the sector basis, and a control circuit checking the sector protection information stored in the second memory cell array whenever the sector to be programmed or erased is selected. Thus, the sector protection information in all the sectors does not have to be latched at the time of power on. The latch circuit equal in number to the sector does not have to be provided. It is thus possible to reduce the number of the circuits drastically and the chip area can be reduced.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: May 29, 2007
    Assignee: Spansion LLC
    Inventors: Kazunari Kido, Minoru Yamashita, Kazuhiro Kurihara, Atsushi Hatakeyama, Hiroaki Wada
  • Patent number: 7221587
    Abstract: The semiconductor device of the present invention includes a column decoder (select and write circuit), which selects multiple pages that are not located adjacently to each other so as to simultaneously program multiple bits in the memory cells of the selected page, when the multiple bits are programmed in the multiple pages. The page is a selection unit and is composed of a given number of the memory cells located on a same word line. An unnecessary stress of programming is not applied to the memory cells that are not to be programmed, by increasing the distance between the memory cells to be programmed simultaneously.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: May 22, 2007
    Assignee: Spansion LLC
    Inventors: Minoru Yamashita, Kazuhiro Kurihara, Hiroaki Wada
  • Patent number: 7206241
    Abstract: The semiconductor device of the present invention includes at least one dummy cell of a programmed state proximately located to an edge of a reference cell array. Thus, the leak current does not flow when a data of the cell on the edge of the reference cell array is read out. The memory cell located around the center of the reference cell array has neighboring cells of the programmed state, and the leak current can be prevented when the data is read out from all the reference cells. Thus, the reference current can be supplied stably.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: April 17, 2007
    Assignee: Spansion LLC
    Inventors: Kazunari Kido, Yasushi Kasa, Minoru Yamashita, Kazuhiro Kurihara, Hiroaki Wada
  • Publication number: 20050276125
    Abstract: A semiconductor device includes a first memory cell array that includes memory cells for storing data and is managed on a sector basis, a second memory cell array including memory cells storing sector protection information on the sector basis, and a control circuit checking the sector protection information stored in the second memory cell array whenever the sector to be programmed or erased is selected. Thus, the sector protection information in all the sectors does not have to be latched at the time of power on. The latch circuit equal in number to the sector does not have to be provided. It is thus possible to reduce the number of the circuits drastically and the chip area can be reduced.
    Type: Application
    Filed: May 11, 2005
    Publication date: December 15, 2005
    Inventors: Kazunari Kido, Minoru Yamashita, Kazuhiro Kurihara, Atsushi Hatakeyama, Hiroaki Wada
  • Publication number: 20050276112
    Abstract: The semiconductor device of the present invention includes at least one dummy cell of a programmed state proximately located to an edge of a reference cell array. Thus, the leak current does not flow when a data of the cell on the edge of the reference cell array is read out. The memory cell located around the center of the reference cell array has neighboring cells of the programmed state, and the leak current can be prevented when the data is read out from all the reference cells. Thus, the reference current can be supplied stably.
    Type: Application
    Filed: May 11, 2005
    Publication date: December 15, 2005
    Inventors: Kazunari Kido, Yasushi Kasa, Minoru Yamashita, Kazuhiro Kurihara, Hiroaki Wada
  • Publication number: 20050254316
    Abstract: The semiconductor device includes a memory cell array that includes memory cells for storing data and is managed on a sector basis, a memory that stores the information determining the activation status, a latch circuit that latches the activation information according to the information stored in the memory, and a circuit that latches the activation information according to the information stored in the memory in the latch circuit. The activation information according to the memory state of the memory is latched at the time of inputting a given command after activation, and it is thus possible to read the information stored in the memory and set the information in the latch circuit certainly.
    Type: Application
    Filed: May 12, 2005
    Publication date: November 17, 2005
    Inventors: Kazunari Kido, Kazuhiro Kurihara, Minoru Yamashita
  • Publication number: 20050254329
    Abstract: The semiconductor device of the present invention includes a column decoder (select and write circuit), which selects multiple pages that are not located adjacently to each other so as to simultaneously program multiple bits in the memory cells of the selected page, when the multiple bits are programmed in the multiple pages. The page is a selection unit and is composed of a given number of the memory cells located on a same word line. An unnecessary stress of programming is not applied to the memory cells that are not to be programmed, by increasing the distance between the memory cells to be programmed simultaneously.
    Type: Application
    Filed: May 11, 2005
    Publication date: November 17, 2005
    Inventors: Minoru Yamashita, Kazuhiro Kurihara, Hiroaki Wada
  • Patent number: 6934194
    Abstract: A nonvolatile memory has a plurality of memory cells, each of the memory cells having a first and a second source/drain areas, a control gate, and an insulating trap layer disposed between the control gate and a channel area lying between the first and the second source/drain areas. The trap layer includes a use bit area in proximity to the first source/drain area, for storing data depending on the presence or absence of electric charge to be trapped, and a non-use bit area in proximity to the second source/drain area, in which the electric charge is trapped while data is held in the use bit area. Preferably, in the state where erasing operation is completed, the non-use bit area is brought into a state where electric charge is trapped therein.
    Type: Grant
    Filed: August 1, 2003
    Date of Patent: August 23, 2005
    Assignee: Fujitsu Limited
    Inventors: Satoshi Takahashi, Minoru Yamashita
  • Patent number: 6914824
    Abstract: A semiconductor memory that prevents a decrease in margin at read time. A bit line in a floating state between a drain in a memory cell to be read and a charged bit line is charged for a certain period of time.
    Type: Grant
    Filed: March 21, 2003
    Date of Patent: July 5, 2005
    Assignee: Fujitsu Limited
    Inventors: Minoru Yamashita, Yuichi Einaga, Kazunari Kido
  • Publication number: 20050000604
    Abstract: An aluminum alloy according to the present invention includes from 4.0 to 6.0% Mg, from 0.3 to 0.6% Mn, from 0.5 to 0.9% Fe, and the balance of Al and inevitable impurities when the entirety is taken as 100% by mass. By appropriately selecting the composition range of Mg, Mn and Fe, it has been possible to micro-finely crystallize Al (Mn, Fe) compounds while inhibiting the growth of primary-crystal Al. As a result, the resulting aluminum alloy is good in terms of the castability, and shows high strength as well as high ductility.
    Type: Application
    Filed: August 30, 2002
    Publication date: January 6, 2005
    Inventors: Hiroshi Kawahara, Yoshihiro Shimizu, Yoshio Sugiyama, Toshio Horie, Hiroaki Iwahori, Yoshihiko Sugimoto, Minoru Yamashita
  • Patent number: 6807433
    Abstract: A mobile communication terminal is provided with a light-emitting element for notifying an unanswered incoming call. When the cancellation of an incoming call is canceled in a state where an incoming call response operation has not been carried out, the mobile communication terminal is brought into the standby state and then the light-emitting element is caused to emit light.
    Type: Grant
    Filed: March 18, 2002
    Date of Patent: October 19, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisashi Oota, Kiyoshi Wagai, Minoru Yamashita
  • Publication number: 20040166575
    Abstract: Strains showing favorable growth in a medium containing 6-ethoxypurine are selected from a population of Bacillus bacteria, and a strain showing high inosine-producing ability is selected from the obtained strains to obtain a Bacillus bacterium having improved inosine-producing ability.
    Type: Application
    Filed: February 6, 2004
    Publication date: August 26, 2004
    Inventors: Misa Tominaga, Keishi Shimazaki, Kiyoshi Matsuno, Minoru Yamashita
  • Patent number: 6765828
    Abstract: A non-volatile semiconductor storage device provided with a boost circuit for setting, for at least a certain period of time, a source line selectively connected to a memory cell to a negative potential, when reading out data from the memory cell is disclosed.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: July 20, 2004
    Assignee: Fujitsu Limited
    Inventor: Minoru Yamashita
  • Publication number: 20040027858
    Abstract: A nonvolatile memory has a plurality of memory cells, each of the memory cells having a first and a second source/drain areas, a control gate, and an insulating trap layer disposed between the control gate and a channel area lying between the first and the second source/drain areas. The trap layer includes a use bit area in proximity to the first source/drain area, for storing data depending on the presence or absence of electric charge to be trapped, and a non-use bit area in proximity to the second source/drain area, in which the electric charge is trapped while data is held in the use bit area. Preferably, in the state where erasing operation is completed, the non-use bit area is brought into a state where electric charge is trapped therein.
    Type: Application
    Filed: August 1, 2003
    Publication date: February 12, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Satoshi Takahashi, Minoru Yamashita
  • Patent number: 6639849
    Abstract: In a nonvolatile semiconductor memory device, first and second dynamic reference cells are subjected to a same rewriting operation as performed to a memory cell. An average reference current is obtained from the first and second dynamic reference cells, and is compared with a current of data read from the memory cell so as to judge a level of the read data. In this configuration, the second dynamic reference cell is programmed according to a threshold value of the first dynamic reference cell.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: October 28, 2003
    Assignee: Fujitsu Limited
    Inventors: Satoshi Takahashi, Minoru Yamashita
  • Publication number: 20030198083
    Abstract: A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.
    Type: Application
    Filed: November 26, 2002
    Publication date: October 23, 2003
    Applicant: Fujitsu Limited
    Inventors: Takao Akaogi, Nobuaki Takashina, Yasushi Kasa, Kiyoshi Itano, Hiromi Kawashima, Minoru Yamashita, Shouichi Kawamura
  • Publication number: 20030179628
    Abstract: A semiconductor memory that prevents a decrease in margin at read time. A bit line in a floating state between a drain in a memory cell to be read and a charged bit line is charged for a certain period of time.
    Type: Application
    Filed: March 21, 2003
    Publication date: September 25, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Minoru Yamashita, Yuichi Einaga, Kazunari Kido
  • Publication number: 20030176205
    Abstract: A mobile communication terminal is provided with a light-emitting element for notifying an unanswered incoming call. When the cancellation of an incoming call is canceled in a state where an incoming call response operation has not been carried out, the mobile communication terminal is brought into the standby state and then the light-emitting element is caused to emit light.
    Type: Application
    Filed: March 18, 2002
    Publication date: September 18, 2003
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hisashi Oota, Kiyoshi Wagai, Minoru Yamashita
  • Publication number: 20030161188
    Abstract: In a nonvolatile semiconductor memory device, first and second dynamic reference cells are subjected to a same rewriting operation as performed to a memory cell. An average reference current is obtained from the first and second dynamic reference cells, and is compared with a current of data read from the memory cell so as to judge a level of the read data. In this configuration, the second dynamic reference cell is programmed according to a threshold value of the first dynamic reference cell.
    Type: Application
    Filed: February 3, 2003
    Publication date: August 28, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Satoshi Takahashi, Minoru Yamashita
  • Patent number: 6611464
    Abstract: A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.
    Type: Grant
    Filed: October 7, 2002
    Date of Patent: August 26, 2003
    Assignee: Fujitsu Limited
    Inventors: Takao Akaogi, Nobuaki Takashina, Yasushi Kasa, Kiyoshi Itano, Hiromi Kawashima, Minoru Yamashita, Shouichi Kawamura