Abstract: A non-volatile semiconductor storage device provided with a boost circuit for setting, for at least a certain period of time, a source line selectively connected to a memory cell to a negative potential, when reading out data from the memory cell is disclosed.

Abstract: A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

Abstract: A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

Abstract: A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

Abstract: A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

Abstract: A non-volatile semiconductor memory device includes a first cell including a first floating-gate type transistor having a first threshold voltage, and a second cell including a second floating-gate type transistor having a second threshold voltage different from the first threshold voltage. Data is stored by a difference between a first current flowing in the first cell and a second current flowing in the second cell.

Abstract: A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.

Abstract: The present invention is a non-volatile memory device, wherein programming or erasing of memory cells is carried out by injecting or removing carriers in floating gates in the memory cells, comprising: a plurality of memory blocks each comprising a plurality of memory cells, respectively; and an erasing circuit for applying an erasing stress in units of the memory blocks and verifying that erasure has been completed in units of memory cells; wherein the erasing circuit applies an erasing stress to the plurality of memory blocks simultaneously until a past erasing stress minimum value for the plurality of memory blocks. According to the aforementioned invention, an erasing stress value, such as a number of erasing stress applications, is recorded for each memory block in past erasing operations, and the minimum erasing stress value of these erasing stress values is recorded.

Abstract: A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.

Abstract: A flash-erasable semiconductor memory device has a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on the floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.

Abstract: A metal sintered body composite material which can exhibit superior seizure resistance even when light metal is softened, and a method for producing the same. The production method uses iron base raw material powder including C and one of Cr, Mo, V, W, Mn, and Si, and comprises the steps of forming and sintering a powder compressed article so as to obtain a porous metal sintered body having a space lattice structure having pores, impregnating the pores of the porous metal sintered body with an aluminum alloy and solidifying the aluminum alloy, applying aging treatment by heating and holding the composite material at an aging treatment temperature range, whereby a metal constituting the porous metal sintered body has a micro-Vickers hardness of 200 to 800.

Abstract: A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.

Abstract: A flash-erasable semiconductor memory device has a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on the floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.

Abstract: A semiconductor memory device has 2.sup.n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2.sup.m (n>m) word lines among the 2.sup.n word lines, and a second unit for not selecting a block of 2.sup.k (m>k) word lines among the 2.sup.m word lines. The second unit does not select the block of 2.sup.k word lines, and selects a block of 2.sup.k word lines prepared outside the 2.sup.n word lines when any one of the 2.sup.k word lines among the 2.sup.m word lines is defective.

Abstract: A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.

Abstract: A semiconductor memory device has 2.sup.n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2.sup.m (n>m) word lines among the 2.sup.n word lines, and a second unit for not selecting a block of 2.sup.k (m>k) word lines among the 2.sup.m word lines. The second unit does not select the block of 2.sup.k word lines, and selects a block of 2.sup.k word lines prepared outside the 2" word lines when any one of the 2.sup.k word lines among the 2.sup.m word lines is defective.

Abstract: A semiconductor memory device has 2.sup.n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2.sup.m (n>m) word lines among the 2.sup.n word lines, and a second unit for not selecting a block of 2.sup.k (m>k) word lines among the 2.sup.m word lines. The second unit does not select the block of 2.sup.k word lines, and selects a block of 2.sup.k word lines prepared outside the 2.sup.n word lines when any one of the 2.sup.k word lines among the 2.sup.m word lines is defective.

Abstract: vibration insulator is provided which includes a vibration insulator section having an outer cylinder, a rubber member which is vulcanization-bonded to the inner peripheral surface of the outer cylinder and an inner cylinder supported by the rubber member, and a bracket for supporting the vibration insulator section, with the thickness of the bracket material being made as small as possible. The bracket is composed of a pair of sheet-metal bracket members holding the axial ends of the vibration insulator. The bracket members include plate-like base sections axially opposed to each other, cylindrical sections which extend axially outward from the base sections and into which the end portions of the outer cylinder are forced, abutting sections extending radially inward from the end edges of the cylindrical sections and abutting the end surfaces of the outer cylinder and joint sections joining the bracket members to each other. A method of manufacturing the vibration insulator bracket is also provided.