Patents by Inventor Mitsuhiko Kitagawa
Mitsuhiko Kitagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9001382Abstract: An image forming system includes an image forming apparatus and an upper device connected to the image forming apparatus. The image forming apparatus includes a first receiving unit for receiving a print mode including a cost priority mode; a first transmission unit for transmitting the print mode to the upper device; a second receiving unit for receiving a print instruction; a print control unit for printing the print data; a duplex print control unit for controlling a printing operation; and a fixing temperature control unit for controlling a fixing temperature. The upper device includes a first storage unit for storing a save setting; a third receiving unit for receiving image data; a second storage unit for storing the print mode; an arrangement print control unit for generating the print data; and a second transmission unit for transmitting the print instruction.Type: GrantFiled: January 24, 2012Date of Patent: April 7, 2015Assignee: Oki Data CorporationInventor: Mitsuhiko Kitagawa
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Patent number: 9000479Abstract: According to one embodiment, a semiconductor device includes a base layer, a second conductivity type semiconductor layer, a first insulating film, and a first electrode. The first insulating film is provided on an inner wall of a plurality of first trenches extending from a surface of the second conductivity type semiconductor layer toward the base layer side, but not reaching the base layer. The first electrode is provided in the first trench via the first insulating film, and provided in contact with a surface of the second conductivity type semiconductor layer. The second conductivity type semiconductor layer includes a first second conductivity type region, and a second second conductivity type region. The first second conductivity type region is provided between the first trenches. The second second conductivity type region is provided between the first second conductivity type region and the base layer, and between a bottom part of the first trench and the base layer.Type: GrantFiled: March 12, 2014Date of Patent: April 7, 2015Assignee: Kabushiki Kaisha ToshibaInventor: Mitsuhiko Kitagawa
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Patent number: 8975690Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of a second conductivity type, a fourth semiconductor region of the first conductivity type, a fifth semiconductor region of the second conductivity type, a first electrode, a second electrode, and a third electrode. The first electrode is provided together with the first region in a first direction, provided together with the third region in a second direction, and has an end portion of the first region side located nearer to the first semiconductor side than a boundary between the second region and the third region. The second electrode is provided between the first electrode and the first region and is in electrical continuity with the fourth region. The third electrode contacts with the fourth region.Type: GrantFiled: August 19, 2013Date of Patent: March 10, 2015Assignee: Kabushiki Kaisha ToshibaInventor: Mitsuhiko Kitagawa
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Publication number: 20150062603Abstract: An information processing apparatus is connected to an image forming apparatus to be capable of communicating with the image forming apparatus. The information processing apparatus includes a storage unit for storing low cost printing information transmitted from the image forming apparatus; a receiving unit for receiving a printing instruction; and a control unit for determining whether first data or second data different from the first data is transmitted to the image forming apparatus according to the low cost printing information stored in the storage unit when the receiving unit receives the printing instruction.Type: ApplicationFiled: November 6, 2014Publication date: March 5, 2015Inventor: Mitsuhiko KITAGAWA
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Publication number: 20150021656Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a first control electrode, a first electrode, a second control electrode, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, and a first insulating film. The first control electrode is provided on or above the first semiconductor region. The first electrode is provided on the first control electrode. The second control electrode is provided on or above the first semiconductor region and includes a first portion which is beside the first control electrode and a second portion which is provided on the first portion and beside the first electrode. The second semiconductor region is provided on the first semiconductor region. A boundary between the first semiconductor region and the second semiconductor region is above the lower end of the first electrode.Type: ApplicationFiled: March 10, 2014Publication date: January 22, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Mitsuhiko Kitagawa
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Publication number: 20150001668Abstract: According to one embodiment, a semiconductor device is provided. The semiconductor device has a first region formed of semiconductor and a second region formed of semiconductor which borders the first region. An electrode is formed to be in ohmic-connection with the first region. A third region is formed to sandwich the first region. A first potential difference is produced between the first and the second regions in a thermal equilibrium state, according to a second potential difference between the third region and the first region.Type: ApplicationFiled: September 16, 2014Publication date: January 1, 2015Inventor: Mitsuhiko KITAGAWA
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Patent number: 8860171Abstract: According to one embodiment, a semiconductor device is provided. The semiconductor device has a first region formed of semiconductor and a second region formed of semiconductor which borders the first region. An electrode is formed to be in ohmic-connection with the first region. A third region is formed to sandwich the first region. A first potential difference is produced between the first and the second regions in a thermal equilibrium state, according to a second potential difference between the third region and the first region.Type: GrantFiled: December 14, 2010Date of Patent: October 14, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Mitsuhiko Kitagawa
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Publication number: 20140191282Abstract: According to one embodiment, a semiconductor device includes a base layer, a second conductivity type semiconductor layer, a first insulating film, and a first electrode. The first insulating film is provided on an inner wall of a plurality of first trenches extending from a surface of the second conductivity type semiconductor layer toward the base layer side, but not reaching the base layer. The first electrode is provided in the first trench via the first insulating film, and provided in contact with a surface of the second conductivity type semiconductor layer. The second conductivity type semiconductor layer includes a first second conductivity type region, and a second second conductivity type region. The first second conductivity type region is provided between the first trenches. The second second conductivity type region is provided between the first second conductivity type region and the base layer, and between a bottom part of the first trench and the base layer.Type: ApplicationFiled: March 12, 2014Publication date: July 10, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Mitsuhiko KITAGAWA
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Patent number: 8710542Abstract: A semiconductor device includes a base layer, a second conductivity type semiconductor layer, a first insulating film, and a first electrode. The first insulating film is provided on an inner wall of a plurality of first trenches extending from a surface of the second conductivity type semiconductor layer toward the base layer side, but not reaching the base layer. The first electrode is provided in the first trench via the first insulating film, and provided in contact with a surface of the second conductivity type semiconductor layer. The second conductivity type semiconductor layer includes first and second regions. The first region is provided between the first trenches. The second region is provided between the first second conductivity type region and the base layer, and between a bottom part of the first trench and the base layer. The second region has less second conductivity type impurities than the first region.Type: GrantFiled: September 21, 2011Date of Patent: April 29, 2014Assignee: Kabushiki Kaisha TosibaInventor: Mitsuhiko Kitagawa
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Publication number: 20140077257Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate, a device portion disposed in the semiconductor substrate, and a junction terminal portion disposed in the semiconductor substrate and having an annular shape surrounding the device portion. The junction terminal portion includes first semiconductor regions of a first conductivity type and second semiconductor regions of a second conductivity type. The first semiconductor regions are adjacent to each other in a circumferential direction of the annular shape of the junction terminal portion, and have a width decreasing with progressing in a direction away from the device portion. The second semiconductor regions are disposed between the first semiconductor regions, and have a width increasing with progressing in the direction away from the device portion.Type: ApplicationFiled: August 20, 2013Publication date: March 20, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Mitsuhiko Kitagawa
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Publication number: 20140077293Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of a second conductivity type, a fourth semiconductor region of the first conductivity type, a fifth semiconductor region of the second conductivity type, a first electrode, a second electrode, and a third electrode. The first electrode is provided together with the first region in a first direction, provided together with the third region in a second direction, and has an end portion of the first region side located nearer to the first semiconductor side than a boundary between the second region and the third region. The second electrode is provided between the first electrode and the first region and is in electrical continuity with the fourth region. The third electrode contacts with the fourth region.Type: ApplicationFiled: August 19, 2013Publication date: March 20, 2014Applicant: Kabushiki Kaisha ToshibaInventor: Mitsuhiko Kitagawa
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Publication number: 20140027858Abstract: A semiconductor device includes: a semiconductor layer having a first end portion and a second end portion; a first main electrode provided on the first end portion and electrically connected to the semiconductor layer; a second main electrode provided on the second end portion and electrically connected to the semiconductor layer; a first gate electrode provided via a first gate insulating film in a plurality of first trenches formed from the first end portion toward the second end portion; and a second gate electrode provided via a second gate insulating film in a plurality of second trenches formed from the second end portion toward the first end portion. Spacing between a plurality of the first gate electrodes and spacing between a plurality of the second gate electrodes are 200 nm or less.Type: ApplicationFiled: October 7, 2013Publication date: January 30, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Mitsuhiko KITAGAWA
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Patent number: 8581298Abstract: A semiconductor device includes: a semiconductor layer having a first end portion and a second end portion; a first main electrode provided on the first end portion and electrically connected to the semiconductor layer; a second main electrode provided on the second end portion and electrically connected to the semiconductor layer; a first gate electrode provided via a first gate insulating film in a plurality of first trenches formed from the first end portion toward the second end portion; and a second gate electrode provided via a second gate insulating film in a plurality of second trenches formed from the second end portion toward the first end portion. Spacing between a plurality of the first gate electrodes and spacing between a plurality of the second gate electrodes are 200 nm or less.Type: GrantFiled: March 15, 2010Date of Patent: November 12, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Mitsuhiko Kitagawa
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Publication number: 20130248886Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having first and second main surfaces, and including a first semiconductor layer of a first conductivity type in the substrate, a second semiconductor layer of a second conductivity type on a surface of the first semiconductor layer on a first main surface side, a third semiconductor layer of the first conductivity type on a surface of the second semiconductor layer, and a fourth semiconductor layer of the second conductivity type on a surface of the first semiconductor layer on a second main surface side. The device further includes a control electrode and a first main electrode on the first main surface side of the substrate, and a second main electrode and a junction termination portion on the second main surface side of the substrate, the junction termination portion having an annular planar shape surrounding the fourth semiconductor layer.Type: ApplicationFiled: January 30, 2013Publication date: September 26, 2013Applicant: Kabushiki Kaisha ToshibaInventor: Mitsuhiko KITAGAWA
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Patent number: 8415711Abstract: According to an embodiment, a semiconductor device includes a first trench being provided in an N+ substrate. An N layer, an N? layer, a P layer, and an N+ layer are formed in a stacked manner to cover the first trench. The semiconductor device includes second and third trenches. The P+ layer is formed to cover the second trench. The trench gates are formed to cover the third trenches.Type: GrantFiled: September 15, 2011Date of Patent: April 9, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Mitsuhiko Kitagawa
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Publication number: 20120194832Abstract: An image forming system includes an image forming apparatus and an upper device connected to the image forming apparatus. The image forming apparatus includes a first receiving unit for receiving a print mode including a cost priority mode; a first transmission unit for transmitting the print mode to the upper device; a second receiving unit for receiving a print instruction; a print control unit for printing the print data; a duplex print control unit for controlling a printing operation; and a fixing temperature control unit for controlling a fixing temperature. The upper device includes a first storage unit for storing a save setting; a third receiving unit for receiving image data; a second storage unit for storing the print mode; an arrangement print control unit for generating the print data; and a second transmission unit for transmitting the print instruction.Type: ApplicationFiled: January 24, 2012Publication date: August 2, 2012Inventor: Mitsuhiko KITAGAWA
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Publication number: 20120074460Abstract: According to an embodiment, a semiconductor device includes a first trench being provided in an N+ substrate. An N layer, an N? layer, a P layer, and an N+ layer are formed in a stacked manner to cover the first trench. The semiconductor device includes second and third trenches. The P+ layer is formed to cover the second trench. The trench gates are formed to cover the third trenches.Type: ApplicationFiled: September 15, 2011Publication date: March 29, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Mitsuhiko KITAGAWA
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Publication number: 20120068221Abstract: A semiconductor device includes a base layer, a second conductivity type semiconductor layer, a first insulating film, and a first electrode. The first insulating film is provided on an inner wall of a plurality of first trenches extending from a surface of the second conductivity type semiconductor layer toward the base layer side, but not reaching the base layer. The first electrode is provided in the first trench via the first insulating film, and provided in contact with a surface of the second conductivity type semiconductor layer. The second conductivity type semiconductor layer includes first and second regions. The first region is provided between the first trenches. The second region is provided between the first second conductivity type region and the base layer, and between a bottom part of the first trench and the base layer. The second region has less second conductivity type impurities than the first region.Type: ApplicationFiled: September 21, 2011Publication date: March 22, 2012Applicant: Kabushiki Kaisha ToshibaInventor: Mitsuhiko KITAGAWA
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Publication number: 20120068222Abstract: According to an embodiment, a semiconductor device includes a first trench being provided in an N+ substrate. An N layer, an N? layer, a P layer, and an N+ layer are formed in a stacked manner to cover the first trench. The semiconductor device includes second and third trenches. The P+ layer is formed to cover the second trench. The trench gates are formed to cover the third trenches.Type: ApplicationFiled: March 18, 2011Publication date: March 22, 2012Applicant: Kabushiki Kaisha ToshibaInventor: Mitsuhiko KITAGAWA
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Publication number: 20120043638Abstract: A semiconductor device includes: a first insulating layer; a semiconductor layer provided on the first insulating layer; a first semiconductor region selectively provided in the semiconductor layer; a second semiconductor region selectively provided in the semiconductor layer and spaced from the first semiconductor region; a first main electrode provided in contact with the first semiconductor region; a second main electrode provided in contact with the second semiconductor region; a second insulating layer provided on the semiconductor layer; a first conductive material provided in the second insulating layer above a portion of the semiconductor layer located between the first semiconductor region and the second semiconductor region; and a second conductive material provided in a trench provided in a portion of the semiconductor layer opposed to the first conductive material, being in contact with the first conductive material, and reaching the first insulating layer.Type: ApplicationFiled: November 2, 2011Publication date: February 23, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Mitsuhiko Kitagawa