Patents by Inventor Mitsuhiko Kitagawa
Mitsuhiko Kitagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6967357Abstract: A voltage-driven power semiconductor device includes a voltage-driven IEGT chip, a collector electrode plate, an emitter electrode plate, and an inductance material. The collector electrode plate is connected to the collector of the IEGT chip, and press-contacts the IEGT chip from its collector side. The emitter electrode plate press-contacts the IEGT chip from its emitter side. The inductance material has an inductance component and connects the emitter of the IEGT chip and the emitter electrode plate. In the voltage-driven power semiconductor device having this arrangement, an induced electromotive force is generated in the inductance material arranged between the emitter of the IEGT chip and the emitter electrode plate. This induced electromotive force can suppress a steep current change (di/dt) upon an OFF operation, and can further suppress a steep voltage change (dv/dt) caused by the current change (di/dt).Type: GrantFiled: October 10, 2000Date of Patent: November 22, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Hironobu Kon, Yoshinori Iwano, Mitsuhiko Kitagawa, Shigeru Hasegawa, Michiaki Hiyoshi
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Publication number: 20050253190Abstract: A semiconductor device comprises a semiconductor substrate; a semiconductor layer provided on the surface of the semiconductor substrate; a base layer provided on the surface of the semiconductor layer; a source layer provided on the surface of the base layer; a trench formed to pass through the source layer, the base layer, and the semiconductor layer from the surface of the source layer, and reaching the semiconductor substrate; a gate electrode provided from the source layer to at least the semiconductor layer within the trench; and an insulator provided between the gate electrode and the base layer so as to fill in the inside of the trench below the gate electrode, the insulator insulating the gate electrode from the base layer, and generating a potential distribution from the gate electrode toward the semiconductor substrate when a voltage is applied to the gate electrode.Type: ApplicationFiled: April 8, 2005Publication date: November 17, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hideki Okumura, Mitsuhiko Kitagawa, Takuma Hara, Takayoshi Ino, Kiyotaka Arai, Satoshi Taji, Masanobu Tsuchitani
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Publication number: 20050230675Abstract: According to the present invention, there is provided a field-effect transistor comprising: a silicon layer formed on an insulating film; a first-conductivity-type base layer formed in said silicon layer; a second-conductivity-type source layer formed in said silicon layer so as to be adjacent to said first-conductivity-type base layer; a second-conductivity-type drain layer formed in said silicon layer so as to be separated from said second-conductivity-type source layer with said first-conductivity-type base layer being interposed therebetween; a gate-to-drain offset layer formed between said first-conductivity-type base layer and said second-conductivity-type drain layer in said silicon layer, and having a resistance higher than that of said first-conductivity-type base layer; and a gate electrode formed on at least a surface of said first-conductivity-type base layer via a gate insulating film, wherein said silicon layer in which said first-conductivity-type base layer is formed is a strained silicon layeType: ApplicationFiled: December 2, 2004Publication date: October 20, 2005Applicant: Kabushiki Kaisha ToshibaInventors: Ryujiro Saso, Mitsuhiko Kitagawa, Takashi Nishimura, Yoshiaki Aizawa
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Publication number: 20040232483Abstract: The present invention provides a MOSFET having a low on-state resistance and a high withstand voltage as well as a small output capacitance (C(gd), etc.). The MOSFET has a p-type base layer 4 and a n-type source layer 5 selectively formed on the surface of the p-type base layer. 4. A n-type drain layer 7 is formed in a position apart from the p-type base layer 4. On the surface of the region between the p-type base layer 4 and the n-type drain layer 7, a n-type drift semiconductor layer 12 and a p-type drift semiconductor layer 13 are alternately arranged from the p-type base layer 4 to the n-type drain layer 7. Further, in the region between the n-type source layer 5 and the n-type drain layer 7, a gate electrode 15 is formed via a gate insulating film 14.Type: ApplicationFiled: June 9, 2004Publication date: November 25, 2004Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Mitsuhiko Kitagawa, Yoshiaki Aizawa
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Patent number: 6777746Abstract: The present invention provides a MOSFET having a low on-state resistance and a high withstand voltage as well as a small output capacitance (C(gd), etc.). The MOSFET has a p-type base layer 4 and a n-type source layer 5 selectively formed on the surface of the p-type base layer 4. A n-type drain layer 7 is formed in a position apart from the p-type base layer 4. On the surface of the region between the p-type base layer 4 and the n-type drain layer 7, a n-type drift semiconductor layer 12 and a p-type drift semiconductor layer 13 are alternately arranged from the p-type base layer 4 to the n-type drain layer 7. Further, in the region between the n-type source layer 5 and the n-type drain layer 7, a gate electrode 15 is formed via a gate insulating film 14.Type: GrantFiled: March 27, 2003Date of Patent: August 17, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuhiko Kitagawa, Yoshiaki Aizawa
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Publication number: 20040094798Abstract: A semiconductor device comprises: a first main electrode; a second main electrode; a semiconductor base region of a first conductivity type; a gate electrode provided in a trench through an insulating film, the trench being formed to penetrate the semiconductor base region; and a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type provided under the semiconductor base region. A flow of a current between the first and second main electrodes when a voltage of a predetermined direction is applied between these electrodes is controllable in accordance with a voltage applied to the gate electrode. A depleted region extends from a junction between the first and the second semiconductor regions reaching the trench.Type: ApplicationFiled: August 29, 2003Publication date: May 20, 2004Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takuma Hara, Mitsuhiko Kitagawa
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Publication number: 20040061106Abstract: A MEMS (micro electro mechanical system) apparatus is equipped with a light-emitting circuit, having a light-emitting device, to emit light; a light-receiving circuit having a series circuit of series-connected light-receiving devices that receive the emitted light to generate a voltage; and a MEMS assembly driven by the generated voltage.Type: ApplicationFiled: July 11, 2003Publication date: April 1, 2004Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Mitsuhiko Kitagawa, Yoshiaki Aizawa
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Publication number: 20030183858Abstract: The present invention provides a MOSFET having a low on-state resistance and a high withstand voltage as well as a small output capacitance (C(gd), etc.). The MOSFET has a p-type base layer 4 and a n-type source layer 5 selectively formed on the surface of the p-type base layer 4. A n-type drain layer 7 is formed in a position apart from the p-type base layer 4. On the surface of the region between the p-type base layer 4 and the n-type drain layer 7, a n-type drift semiconductor layer 12 and a p-type drift semiconductor layer 13 are alternately arranged from the p-type base layer 4 to the n-type drain layer 7. Further, in the region between the n-type source layer 5 and the n-type drain layer 7, a gate electrode 15 is formed via a gate insulating film 14.Type: ApplicationFiled: March 27, 2003Publication date: October 2, 2003Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Mitsuhiko Kitagawa, Yoshiaki Aizawa
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Patent number: 6236069Abstract: Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.Type: GrantFiled: June 23, 1998Date of Patent: May 22, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Shinohe, Kazuya Nakayama, Minami Takeuchi, Masakazu Yamaguchi, Mitsuhiko Kitagawa, Ichiro Omura, Akio Nakagawa
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Patent number: 6147368Abstract: A voltage-driven power semiconductor device includes a voltage-driven IEGT chip, a collector electrode plate, an emitter electrode plate, and an inductance material. The collector electrode plate is connected to the collector of the IEGT chip, and press-contacts the IEGT chip from its collector side. The emitter electrode plate press-contacts the IEGT chip from its emitter side. The inductance material has an inductance component and connects the emitter of the IEGT chip and the emitter electrode plate. In the voltage-driven power semiconductor device having this arrangement, an induced electromotive force is generated in the inductance material arranged between the emitter of the IEGT chip and the emitter electrode plate. This induced electromotive force can suppress a steep current change (di/dt) upon an OFF operation, and can further suppress a steep voltage change (dv/dt) caused by the current change (di/dt).Type: GrantFiled: July 14, 1998Date of Patent: November 14, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Hironobu Kon, Yoshinoro Iwano, Mitsuhiko Kitagawa, Shigeru Hasegawa, Michiaki Hiyoshi
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Patent number: 5838026Abstract: An insulated-gate semiconductor device comprises a P type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.Type: GrantFiled: March 28, 1997Date of Patent: November 17, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuhiko Kitagawa, Ichiro Omura, Akio Nakagawa, Norio Yasuhara, Tomoki Inoue
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Patent number: 5796125Abstract: A high breakdown voltage semiconductor device. The device includes a semiconductor substrate, an insulating film formed on the semiconductor substrate, an active region formed on the insulating film, drain and base regions formed in a surface portion of the active region, and a source region formed in a surface portion of the base region. First and second gate insulating films are formed on inner surfaces of first and second grooves penetrating the base region so as to come in contact with the source region and reaching the active region, with first and second electrodes being buried in the first and second grooves. Two or more channel regions are formed in a MOS structure constructed by the gate insulating film, the gate electrode, the source region, the base region and the active region.Type: GrantFiled: September 15, 1995Date of Patent: August 18, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Tomoko Matsudai, Mitsuhiko Kitagawa, Akio Nakagawa
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Patent number: 5793065Abstract: Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.Type: GrantFiled: June 7, 1995Date of Patent: August 11, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Shinohe, Kazuya Nakayama, Minami Takeuchi, Masakazu Yamaguchi, Mitsuhiko Kitagawa, Ichiro Omura, Akio Nakagawa
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Patent number: 5689121Abstract: An insulated-gate semiconductor device comprises a P type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.Type: GrantFiled: June 7, 1995Date of Patent: November 18, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuhiko Kitagawa, Ichiro Omura, Akio Nakagawa, Norio Yasuhara, Tomoki Inoue
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Patent number: 5637909Abstract: A bipolar transistor is formed on a silicon substrate having a silicon oxide film. An n-silicon layer having a top surface of a (100) plane is formed on the silicon oxide film and is used as a collector layer. An end face constituted by a (111) plane is formed on the end portion of the collector layer by etching, using an aqueous KOH solution. A B-doped p-silicon layer is formed on the end face by epitaxial growth and is used as a base layer. Furthermore, an As-doped n-silicon layer is formed on the base layer and is used as an emitter layer. Electrodes are respectively connected to the collector, base, and emitter layers.Type: GrantFiled: January 2, 1996Date of Patent: June 10, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Hiroomi Nakajima, Yasuhiro Katsumata, Hiroshi Iwai, Toshihiko Iinuma, Kazumi Inou, Mitsuhiko Kitagawa, Kouhei Morizuka, Akio Nakagawa, Ichiro Omura
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Patent number: 5585651Abstract: An insulated-gate semiconductor device comprises a p type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.Type: GrantFiled: June 7, 1995Date of Patent: December 17, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuhiko Kitagawa, Ichiro Omura, Akio Nakagawa, Norio Yasuhara, Tomoki Inoue
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Patent number: 5554862Abstract: In a power semiconductor device, an n-base is formed on a p-emitter layer. On the n-base layer, a p-base layer, an n-emitter layer, and a high-concentration p-layer are formed laterally. In the p-base layer, an n-source layer is formed a specified distance apart from the n-emitter layer. In the n-emitter layer, a p-source layer is formed a specified distance apart from the high-concentration p-layer. A first gate electrode is formed via a first gate insulating film on the region sandwiched by the n-source layer and the n-emitter layer. A second gate electrode is formed via a second gate insulating film on the region sandwiched by the high-concentration p-layer and the p-source layer. On the p-emitter layer, a first main electrode is formed. A second main electrode is formed so as to be in contact with the p-base layer, the n-source layer, and the p-source layer.Type: GrantFiled: January 19, 1994Date of Patent: September 10, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Ichiro Omura, Mitsuhiko Kitagawa, Kazuya Nakayama, Masakazu Yamaguchi
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Patent number: 5510647Abstract: A bipolar transistor is formed on a silicon substrate having a silicon oxide film. An n-silicon layer having a top surface of a (100) plane is formed on the silicon oxide film and is used as a collector layer. An end face constituted by a (111) plane is formed on the end portion of the collector layer by etching, using an aqueous KOH solution. A B-doped p-silicon layer is formed on the end face by epitaxial growth and is used as a base layer. Furthermore, an As-doped n-silicon layer is formed on the base layer and is used as an emitter layer. Electrodes are respectively connected to the collector, base, and emitter layers.Type: GrantFiled: March 15, 1994Date of Patent: April 23, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Hiroomi Nakajima, Yasuhiro Katsumata, Hiroshi Iwai, Toshihiko Iinuma, Kazumi Inou, Mitsuhiko Kitagawa, Kouhei Morizuka, Akio Nakagawa, Ichiro Omura
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Patent number: 5464994Abstract: Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.Type: GrantFiled: August 16, 1994Date of Patent: November 7, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Shinohe, Kazuya Nakayama, Minami Takeuchi, Masakazu Yamaguchi, Mitsuhiko Kitagawa, Ichiro Omura, Akio Nakagawa
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Patent number: 5448083Abstract: An insulated-gate semiconductor device comprises a P type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby-forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.Type: GrantFiled: June 15, 1994Date of Patent: September 5, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuhiko Kitagawa, Ichiro Omura, Akio Nakagawa, Norio Yasuhara, Tomoki Inoue