Abstract: Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.

Abstract: A semiconductor device having a bipolar MOS composite element pellet suitable for a compression structure. In this pellet, a semiconductor substrate on which a MOS composite element is formed is electrically connected to an external part by an electrode plate compressed to the substrate.

Abstract: A self turn-off power semiconductor device includes a P type emitter layer, a high resistive N type base layer, a P type base layer and a MOS channel structure for injecting electrons into the N type base layer. A series of trench-like grooves are formed in the top surface of a substrate constituting the N type base layer at a constant interval. Insulated gate electrodes are buried in these grooves. The injection efficiency of electrons into the base layer is enhanced by locally controlling the flow of holes in the N type base layer. Controlling the flow of holes is achieved by specifically arranging the width of a hole-bypass path among the grooves, the trench width and the placement distance of the grooves, thereby causing the accumulation of carriers to increase in the base layer to decrease the on-resistance of the device.

Abstract: A GTO thyristor includes a p-type emitter layer, an n-type base layer, a p-type base layer and an n-type emitter layer. An additional n-type layer is formed on the p-type base layer next to the n-type emitter layer An additional p.sup.+ -type layer is formed on the additional n-type layer and stretches to the n-type emitter layer. An anode electrode and a cathode electrode are disposed respectively on the n-type emitter layer and the p-type base layer. The n-type emitter layer and the additional p.sup.+ -type layer are connected with each other by a floating electrode. A first gate electrode is disposed on the additional p.sup.+ -type layer, additional n-type layer and p-type base layer with an insulating film interposed therebetween so as to form a first FET. A second gate electrode is disposed on the n-type base layer, p-type base layer and n-type emitter layer with an insulating film interposed therebetween so as to form a second FET.

Abstract: A mixture of at least two types of charged particles of ions having the same value obtained by dividing the electric charge of an ion by the mass of the ion, i.e., a mixture of charged particles including hydrogen molecular ions H.sub.2.sup.+ and deuterium ions D.sup.+, is accelerated in a charged particle accelerator. Since the mass spectrograph unit in the accelerator cannot divide the hydrogen molecular ions H.sub.2.sup.+ and the deuterium ion D.sup.+, both ions are accelerated together. When the hydrogen molecular ion H.sub.2.sup.+ collides against a silicon substrate, it is divided into two hydrogen ions 2H.sup.+. Since the hydrogen ion H.sup.+ and the deuterium ion D.sup.+ have different ranges in silicon, two regions including a great number of crystal defects are formed in the silicon substrate in one ion irradiating step. As a result, at least three regions of different lifetimes of carriers are formed at different depths of the semiconductor substrate.

Abstract: In a photothyristor, a main thyristor consisting of a P emitter layer, an N base layer, a P gate base layer and an N emitter layer is formed on a semiconductor substrate. Also a pilot thyristor surrounded with the main thyristor and consisting of a P emitter layer, an N base layer, a P gate base layer and an N emitter layer is formed. In the P gate base layer, a trigger light irradiation surface including the inner surface of a recess is formed on the center of the pilot thyristor. In the N base layer, a crystal defect layer is formed under the trigger light irradiation surface by the irradiation with a radiant ray. A breakdown voltage to protect the thyristor from overvoltage is controlled by the crystal defect layer.

Abstract: Phosphorus is doped into one of the major surfaces of an n-type silicon semiconductor substrate, and boron is doped into the other major surface. Thereafter, the structure is diffused into the surface regions of the substrate at a high temperature and for a long time, so that an n-buffer layer is formed in the first major surface, and a p-base layer is formed in the second major surface. Impurity of n-type is diffused into the p-base layer, to form an n-emitter layer. Impurity of p-type is diffused into the n-buffer layer, to selectively form p-emitter layer. Further, n-type impurity is diffused into the n-buffer layer, to form n-type anode short layer.

Abstract: According to this invention, a compression contacted semiconductor device is characterized by including a semiconductor pellet having main electrodes formed a first major surface of one surface side and a second major surface of another surface side, and electrode posts arranged on at least one major surface of the semiconductor pellet through an electrode member to sandwich the semiconductor pellet to compress the electrodes of the first and second major surfaces, wherein a crystal defect density is distributed within a surface of the semiconductor pellet so that a carrier lifetime of at least heat generating portions in the surface of the semiconductor pellet which do not sufficiently conduct heat to the electrode posts is shorter than a carrier lifetime of major heat generating portions which sufficiently conduct heat to the electrode posts. For this reason, current in the heat generating portions which do not sufficiently conduct heat to the electrode members is decreased.

Abstract: A p-type emitter layer 2 is formed in one surface portion of an n.sup.- -type base layer 1 of high resistance. p.sup.+ -type contact layers 2b and n.sup.+ -type current blocking layers 6 are formed in a preset area ratio in the surface area of the p-type emitter layer. A cathode electrode 4 is formed in contact with the contact layer 2b as well as the current blocking layer 6 of the pn junction diode section. With this cathode structure, the electron injection in the ON state can be suppressed so as to reduce the carrier concentration of a portion of the n.sup.- -type base layer 1 lying on the cathode side, and the parasitic transistor effect caused at the time of reverse recovery can be suppressed by provision of the current blocking layer 6.

Abstract: Phosphorus is doped into one of the major surfaces of an n-type silicon semiconductor substrate, and boron is doped into the other major surface. Thereafter, the structure is diffused into the surface regions of the substrate at a high temperature and for a long time, so that an n-buffer layer is formed in the first major surface, and a p-base layer is formed in the second major surface. Impurity of n-type is diffused into the p-base layer, to form an n-emitter layer. Impurity of p-type is diffused into the n-buffer layer, to selectively form p-emitter layer. Further, n-type impurity is diffused into the n-buffer layer, to form n-type anode short layer.

Abstract: A semiconductor switching apparatus includes a member for radiating heat generated from semiconductor switching element chips and for reducing a thermal stress. The lengths of gate electrode wires are equally set. The semiconductor switching apparatus has a large capacity and good switching characteristics.

Abstract: A crimp-type semiconductor device having a non-alloy structure according to this invention has a silicon pellet including a plurality of cathode electrodes and a plurality of gate electrodes arranged to be alternately staggered with the cathode electrodes at the cathode side, and an anode electrode at the anode side. The cathode electrodes are crimped by a cathode electrode post via an electrode member constituted by a thin soft-metal plate and a hard metal plate. The anode electrode is crimped by an anode electrode post via an electrode member. Opposing surfaces of the electrodes, the electrode members, and the electrode posts are not bonded to but crimped in contact with each other. The electrode members are formed to cover the entire surfaces of the cathode electrode and the anode electrode, respectively, and the entire surface of the cathode electrode post and the anode electrode post, respectively.