Patents by Inventor Mitsuo Usami

Mitsuo Usami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020052877
    Abstract: The technology includes the steps of: associating material-object identification code identifying each individual material object with material-object information representing information about material object identified by identification code and storing identification code and material-object information in material-object information database in each of business categories; sending code and information stored in database in each business category; integrating items of information having same code with each other among codes and items of information received from database in each business category to generate integrated material-object information, associating identification code with integrated material-object information identified by code and storing identification code and integrated material-object information in integrated database; requesting to send integrated material-object information associated with given identification code; reading requested integrated material-object information from integrat
    Type: Application
    Filed: August 17, 2001
    Publication date: May 2, 2002
    Inventors: Chikashi Okamoto, Kazuo Takaragi, Yasuko Fukuzawa, Hideki Tokuyama, Mitsuo Usami
  • Patent number: 6379998
    Abstract: A process of contacting sides of a plurality of chips having semiconductor elements formed in a substrate surface, directly to each other on the same {111} crystal plane.
    Type: Grant
    Filed: January 21, 1993
    Date of Patent: April 30, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Ohta, Hideo Miura, Mitsuo Usami, Masatsugu Kametani, Munetoshi Zen, Noriaki Okamoto
  • Publication number: 20020048907
    Abstract: The semiconductor wafer is made thin without any cracks and warp under good workability. The semiconductor wafer thinning process includes the first step of preparing a carrier 1 formed of a base 1a and a suction pad 1b provided on one surface of the base 1a or formed of a base film with an adhesive, the second step of bonding a semiconductor wafer to the carrier 1 in such a manner that a rear surface of the semiconductor wafer 2 with no circuit elements formed therein is opposite to the carrier to form a wafer composite 10, and the third step of holding the carrier of the wafer composite 10 with its semiconductor wafer 2 side up and spin-coating an etchant on the rear surface of the semiconductor wafer 2 thereby to make the semiconductor wafer 2 thin.
    Type: Application
    Filed: November 26, 2001
    Publication date: April 25, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Toshio Miyamoto, Kunihiro Tsubosaki, Mitsuo Usami
  • Publication number: 20020034860
    Abstract: The semiconductor wafer is made thin without any cracks and warp under good workability. The semiconductor wafer thinning process includes the first step of preparing a carrier 1 formed of a base 1a and a suction pad 1b provided on one surface of the base 1a or formed of a base film with an adhesive, the second step of bonding a semiconductor wafer to the carrier 1 in such a manner that a rear surface of the semiconductor wafer 2 with no circuit elements formed therein is opposite to the carrier to form a wafer composite 10, and the third step of holding the carrier of the wafer composite 10 with its semiconductor wafer 2 side up and spin-coating an etchant on the rear surface of the semiconductor wafer 2 thereby to make the semiconductor wafer 2 thin.
    Type: Application
    Filed: November 26, 2001
    Publication date: March 21, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Toshio Miyamoto, Kunihiro Tsubosaki, Mitsuo Usami
  • Publication number: 20020027274
    Abstract: A thin-film semiconductor device comprising at least a semiconductor element and a wiring is disclosed. A thin film of a protective insulating material is formed on the lower surface of the semiconductor element, and a substrate is bonded on the lower surface of the thin film. A method for fabricating the thin-film semiconductor device is also disclosed, in which a thin-film semiconductor circuit is formed on a silicon-on-insulator wafer, the silicon substrate on the reverse side of the silicon-on-insulator wafer is etched off, a thin-film semiconductor chip is formed and attached to the substrate, and the thin-film semiconductor chip and the substrate are wired to each other by printing.
    Type: Application
    Filed: September 18, 2001
    Publication date: March 7, 2002
    Inventors: Mitsuo Usami, Takashi Tase
  • Publication number: 20020016020
    Abstract: The existing IC cards have a disadvantage of difficulty of mass production because an IC chip is supplied on a substrate one at a time. The present invention provides a method of manufacturing by placing a positioning jig having a plurality of openings each of which has a size fit with a semiconductor device, providing a plurality of semiconductor devices on said jig to house the devices into the openings, and fixing on a substrate then cutting the substrate to provide independent electronic devices. When the semiconductor device is in a form of chip, a support member attached to the chip will facilitate the handling of chips.
    Type: Application
    Filed: March 28, 2001
    Publication date: February 7, 2002
    Inventor: Mitsuo Usami
  • Patent number: 6342434
    Abstract: A semiconductor wafer is made thin without any cracks or warp under good workability. The semiconductor wafer thinning process includes the first step of preparing a carrier formed of a base and a suction pad provided on one surface of the base or formed of a base film with an adhesive, the second step of bonding a semiconductor wafer to the carrier in such a manner that a rear surface of the semiconductor wafer with no circuit elements formed therein is opposite to the carrier to form a wafer composite, and the third step of holding the carrier of the wafer composite with its semiconductor wafer side up and spin-coating an etchant on the rear surface of the semiconductor wafer thereby to make the semiconductor wafer thin.
    Type: Grant
    Filed: June 1, 1998
    Date of Patent: January 29, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Toshio Miyamoto, Kunihiro Tsubosaki, Mitsuo Usami
  • Publication number: 20010046730
    Abstract: In a method of designing/manufacturing a plurality of semiconductor integrated circuit devices having built-in ROMs each storing different data on a single wafer, a ROM pattern is formed in combination with a pattern that is common to a plurality of semiconductor integrated circuit devices other than the ROM pattern.
    Type: Application
    Filed: May 25, 2001
    Publication date: November 29, 2001
    Inventors: Toshio Suzuki, Mitsuo Usami
  • Publication number: 20010028103
    Abstract: Concerning a plurality of second bonding pads that are electrically connected with a plurality of first bonding pads provided on an IC chip and having a predetermined narrow pitch, a technique is disclosed that allows the plurality of second pads to be provided on the IC chip. This makes it possible to provide the second pads at desired positions. Accordingly, it becomes possible to form, by printing with a low accuracy, respective interconnections that connect the plurality of second pads with a plurality of electrodes provided on a substrate. Also, matching of positions is executed between the plurality of second pads and the plurality of electrodes formed on the substrate by printing. This matching makes it possible to electrically connect the second pads with the electrodes provided on the substrate in a such a manner that they are opposed to each other.
    Type: Application
    Filed: May 22, 2001
    Publication date: October 11, 2001
    Applicant: Hitachi, Ltd.
    Inventor: Mitsuo Usami
  • Publication number: 20010025884
    Abstract: In a data carrier information reading method for reading data from a data carrier including a data storage device and a data communicator device, a state in which a plurality of sheets of objective items with data carriers attached thereto are accumulated in a pile in an order is shifted to a state in which any of positions respectively of the data carriers are not overlapped with any one of the objective items to thereby read information from the data carriers of the objective items in the shifted state.
    Type: Application
    Filed: February 20, 2001
    Publication date: October 4, 2001
    Inventors: Masaya Miura, Yutaka Miyazaki, Mitsuo Usami, Takashi Yoshida
  • Publication number: 20010026220
    Abstract: A carrier case for accommodating paper sheets, cards or the like having radio frequency data carriers attached thereto or watermarked therein. A device is provided for reading out information from the radio frequency data carriers while eliminating the need for externally removing the paper sheets, cards or the like having the radio frequency data carriers attached thereto or watermarked therein. The carrier case is provided therein with an opening for insertion of the data reading device, and is also provided with a movable divider plate. When it is desired to read out data from the radio frequency data carriers, the divider plate is tilted so that the data reading device can read out the data from the data carriers with a good sensitivity in a relationship contacted with the radio frequency data carriers or not contacted therewith.
    Type: Application
    Filed: February 16, 2001
    Publication date: October 4, 2001
    Inventors: Masaya Miura, Yutaka Miyazaki, Mitsuo Usami, Takashi Yoshida
  • Patent number: 6291877
    Abstract: A thin-film semiconductor device comprising at least a semiconductor element and a wiring is disclosed. A thin film of a protective insulating material is formed on the lower surface of the semiconductor element, and a substrate is bonded on the lower surface of the thin film. A method for fabricating the thin-film semiconductor device is also disclosed, in which a thin-film semiconductor circuit is formed on a silicon-on-insulator wafer, the silicon substrate on the reverse side of the silicon-on-insulator wafer is etched off, a thin-film semiconductor chip is formed and attached to the substrate, and the thin-film semi conductor chip and the substrate are wired to each other by printing.
    Type: Grant
    Filed: April 4, 2000
    Date of Patent: September 18, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Mitsuo Usami, Takashi Tase
  • Publication number: 20010012645
    Abstract: A semiconductor device manufacturing method for packaging a thin semiconductor chip in an economical manner. A semiconductor chip having one electrode terminal, a first member having a first conductor on its surface, and a second member having a second conductor on its surface are prepared. The first and second members are positioned such that the first and second conductors face to each other, and the semiconductor chip is held between the members. In this arrangement, one of the first and second conductors is in electrical contact with the first electrode.
    Type: Application
    Filed: February 5, 2001
    Publication date: August 9, 2001
    Inventor: Mitsuo Usami
  • Patent number: 6259158
    Abstract: Concerning a plurality of second bonding pads that are electrically connected with a plurality of first bonding pads provided on an IC chip and having a predetermined narrow pitch, a technique is disclosed that allows the plurality of second pads to be provided on the IC chip. This makes it possible to provide the second pads at desired positions. Accordingly, it becomes possible to form, by printing with a low accuracy, respective interconnections that connect the plurality of second pads with a plurality of electrodes provided on a substrate. Also, matching of positions is executed between the plurality of second pads and the plurality of electrodes formed on the substrate by printing. This matching makes it possible to electrically connect the second pads with the electrodes provided on the substrate in a such a manner that they are opposed to each other.
    Type: Grant
    Filed: June 11, 1999
    Date of Patent: July 10, 2001
    Assignee: Hitachi, Ltd.
    Inventor: Mitsuo Usami
  • Patent number: 6239483
    Abstract: Condenser (114), coil (115) and thin-thickness integrated circuit (312) are placed between the upper cover sheet (117) and the lower cover sheet (118), and adhesive (119) is filled into the space among them, whereby a card is fabricated. Because condenser (114), coil (115) and thin-thickness integrated circuit (312) are extremely thin, the resulting semiconductor device is strong to bending and highly reliable at a low cost.
    Type: Grant
    Filed: April 25, 2000
    Date of Patent: May 29, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Mitsuo Usami, Kunihiro Tsubosaki, Masaru Miyazaki
  • Publication number: 20010000079
    Abstract: A semiconductor chip (105′) and a substrate (102) are bonded with an organic adhesive layer (409) containing conductive particles (406), and a pad (405) and an electrode (412) are mutually, electrically connected through the conductive particles (406).
    Type: Application
    Filed: December 5, 2000
    Publication date: March 29, 2001
    Inventors: Mitsuo Usami, Kunihiro Tsubosaki, Kunihiko Nishi
  • Patent number: 6166911
    Abstract: Provided is a semiconductor assembly, comprising a circuit board (1) including a conductor circuit (4), the conductor circuit including connecting pads, a semiconductor chip (2) provided with connecting terminals provided on a first surface thereof, and mounted on the circuit board, a casing (5) covering the circuit board, wherein the connecting pads of the conductor circuit and the connecting terminals of the semiconductor chip are disposed in mutually opposing relationship, and are connected with each other by an electroconductive bonding agent, a neutral plane of the semiconductor chip substantially coinciding with an overall neutral plane of the semiconductor assembly.
    Type: Grant
    Filed: November 20, 1997
    Date of Patent: December 26, 2000
    Assignees: Hitachi, Ltd., Hitachi Chemical Company, Ltd.
    Inventors: Mitsuo Usami, Kunihiko Nishi, Yoshikatsu Mikami, Masakatsu Suzuki
  • Patent number: 6162701
    Abstract: A semiconductor chip (105') and a substrate (102) are bonded with an organic adhesive layer (409) containing conductive particles (406), and a pad (405) and an electrode (412) are mutually, electrically connected through the conductive particles (406).The semiconductor chip (105') is formed by contacting a semiconductor wafer (105) attached to a tape (107) with an etchant while rotating the semiconductor wafer (105) within an in-plane direction at a high speed or reciprocating the wafer (105) laterally to uniformly etch the semiconductor wafer (105) thereby reducing the thickness thereof, and dicing the thus reduced wafer. The resultant thin chip (105') is hot-pressed by means of a heating head (106) for bonding on the substrate (102).In this way, a thin semiconductor chip can be formed stably at low costs and bonded on a substrate without causing any crack of the chip, thereby obtaining a semiconductor device which is unlikely to break owing to the bending stress from outside.
    Type: Grant
    Filed: April 12, 1999
    Date of Patent: December 19, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Mitsuo Usami, kunihiro Tsubosaki, Kunihiko Nishi
  • Patent number: 6140697
    Abstract: Condenser (114), coil (115) and thin-thickness integrated circuit (312) are placed between the upper cover sheet (117) and the lower cover sheet (118), and adhesive (119) is filled into the space among them, whereby a card is fabricated. Because condenser (114), coil (115) and thin-thickness integrated circuit (312) are extremely thin, the resulting semiconductor device is strong to bending and highly reliable at a low cost.
    Type: Grant
    Filed: October 12, 1999
    Date of Patent: October 31, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Mitsuo Usami, Kunihiro Tsubosaki, Masaru Miyazaki
  • Patent number: 6051877
    Abstract: A thin-film semiconductor device comprising at least a semiconductor element and a wiring is disclosed. A thin film of a protective insulating material is formed on the lower surface of the semiconductor element, and a substrate is bonded on the lower surface of the thin film. A method for fabricating the thin-film semiconductor device is also disclosed, in which a thin-film semiconductor circuit is formed on a silicon-on-insulator wafer, the silicon substrate on the reverse side of the silicon-on-insulator wafer is etched off, a thin-film semiconductor chip is formed and attached to the substrate, and the thin-film semiconductor chip and the substrate are wired to each other by printing.
    Type: Grant
    Filed: July 3, 1997
    Date of Patent: April 18, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Mitsuo Usami, Takashi Tase