Abstract: A well of a first type of conductivity is formed in a semiconductor substrate, and wells of a second type of conductivity are formed in the well of the first type of conductivity at a distance from one another. By an implantation of dopants, a doped region of the second type of conductivity is formed in the well of the first type of conductivity between the wells of the second type of conductivity and at a distance from the wells of the second type of conductivity. Source/drain contacts are applied to the wells of the second type of conductivity, and a gate dielectric and a gate electrode are arranged above regions of the well of the first type of conductivity that are located between the wells of the second type of conductivity and the doped region of the second type of conductivity.

Abstract: An aperture system of an electron beam apparatus includes a plurality of apertures each including a first area including at least one through hole allowing an electron beam to pass therethrough and a second area disposed outside the first area and including first and second alignment keys, wherein two apertures, among the plurality of apertures, include the first alignment keys arranged in mutually overlapping positions and having the same size, and an aperture, excluding the two apertures, among the plurality of apertures, includes the second alignment keys arranged to overlap the first alignment keys and having an area larger than an area of the first alignment keys.

Abstract: Provided is a wireless power reception device including: a gate driver for generating a gate signal for switching between a turn-on voltage and a turn-off voltage; a rectifier connected to both ends of an inductor and including FETs whose on/off states are controlled by the gate signal; a rectifier output detection unit for sensing an output value of the rectifier; and an impedance control unit for controlling an impedance of the rectifier by controlling at least one of a duty ratio of the gate signal and a turn-on voltage for turning on the FET based on the output value.

Abstract: An aperture system of an electron beam apparatus includes a plurality of apertures each including a first area including at least one through hole allowing an electron beam to pass therethrough and a second area disposed outside the first area and including first and second alignment keys, wherein two apertures, among the plurality of apertures, include the first alignment keys arranged in mutually overlapping positions and having the same size, and an aperture, excluding the two apertures, among the plurality of apertures, includes the second alignment keys arranged to overlap the first alignment keys and having an area larger than an area of the first alignment keys.

Abstract: The field effect transistor device comprises a substrate (1) of semiconductor material, a body well of a first type of electric conductivity in the substrate, a source region in the body well, the source region having an opposite second type of electric conductivity, a source contact (3) on the source region, a body contact region of the first type of electric conductivity in the body well, a body contact (5) on the body contact region, and a gate electrode layer (2) partially overlapping the body well. A portion (2*) of the gate electrode layer (2) is present between the source contact (3) and the body contact (5).

Abstract: The field effect transistor device comprises a substrate (1) of semiconductor material, a body well of a first type of electric conductivity in the substrate, a source region in the body well, the source region having an opposite second type of electric conductivity, a source contact (3) on the source region, a body contact region of the first type of electric conductivity in the body well, a body contact (5) on the body contact region, and a gate electrode layer (2) partially overlapping the body well. A portion (2*) of the gate electrode layer (2) is present between the source contact (3) and the body contact (5).

Abstract: The present invention relates to a core drill apparatus which is mounted to a working boom of an excavator so as to drill rock or a concrete structure and, more particularly, to a core drill apparatus for installation in an excavator, which comprises a ring gear and a plurality of elevation cylinders that are connected to and installed in a working support frame mounted to the end of a working boom of an excavator so as to rotate the working support frame, and at the same time, is configured to support the working frame while adjusting the height of the slope using the elevation cylinders when the working frame is supported on an inclined work surface. Therefore, the present invention enables a drilling bit provided in the working support frame to stably drill a structure regardless of the inclination of a work surface to be drilled, and can thus significantly improve the efficiency of a drilling operation.

Abstract: A well of a first type of conductivity is formed in a semiconductor substrate, and wells of a second type of conductivity are formed in the well of the first type of conductivity at a distance from one another. By an implantation of dopants, a doped region of the second type of conductivity is formed in the well of the first type of conductivity between the wells of the second type of conductivity and at a distance from the wells of the second type of conductivity. Source/drain contacts are applied to the wells of the second type of conductivity, and a gate dielectric and a gate electrode are arranged above regions of the well of the first type of conductivity that are located between the wells of the second type of conductivity and the doped region of the second type of conductivity.

Abstract: The symmetric LDMOS transistor comprises a semiconductor substrate (1), a well (2) of a first type of conductivity in the substrate, and wells (3) of an opposite second type of conductivity. The wells (3) of the second type of conductivity are arranged at a distance from one another. Source/drain regions (4) are arranged in the wells of the second type of conductivity. A gate dielectric (7) is arranged on the substrate, and a gate electrode (8) on the gate dielectric. A doped region (10) of the second type of conductivity is arranged between the wells of the second type of conductivity at a distance from the wells. The gate electrode has a gap (9) above the doped region (10), and the gate electrode overlaps regions that are located between the wells (3) of the second type of conductivity and the doped region (10).

Abstract: Disclosed herein is a pad coated with coffee which includes: an outer cover which comes into direct contact with the vagina of a woman; a coating layer which is formed below the outer cover and smells of coffee; an absorber which is laid below the coating layer to absorb secretions; and a waterproof outer cover which is laid below the absorber to prevent the secretions absorbed into the absorber from leaking out, wherein coffee powder is coated on the coating layer.

Abstract: Disclosed herein is a pad coated with coffee which includes: an outer cover which comes into direct contact with the vagina of a woman; a coating layer which is formed below the outer cover and smells of coffee; an absorber which is laid below the coating layer to absorb secretions; and a waterproof outer cover which is laid below the absorber to prevent the secretions absorbed into the absorber from leaking out, wherein coffee powder is coated on the coating layer.

Abstract: A semiconductor body (10) comprises a field-effect transistor (11). The field-effect transistor (11) comprises a drain region (12) of a first conduction type, a source region (13) of the first conduction type, a drift region (16) and a channel region (14) of a second conduction type which is opposite to the first conduction type. The drift region (16) comprises at least two stripes (15, 32) of the first conduction type which extend from the drain region (12) in a direction towards the source region (13). The channel region (14) is arranged between the drift region (16) and the source region (13).

Abstract: The p-channel LDMOS transistor comprises a semiconductor substrate (1), an n well (2) of n-type conductivity in the substrate, and a p well (3) of p-type conductivity in the n well. A portion of the n well is located under the p well. A drain region (4) of p-type conductivity is arranged in the p well, and a source region (9) of p-type conductivity is arranged in the n well. A gate dielectric (7) is arranged on the substrate, and a gate electrode (8) is arranged on the gate dielectric. A body contact region (14) of n-type conductivity is arranged in the n well. A p implant region (17) is arranged in the n well under the p well in the vicinity of the p well. The p implant region locally compensates n-type dopants of the n well.

Abstract: A lens actuating module for realizing focus adjustment and optical zooming. The lens actuating module includes a rod which is disposed on one side of a lens barrel on which at least one lens is mounted, and has an axis direction corresponding to an optical axis direction of the lens barrel, a driving force transmission member which has a conjoining recess to be conjoined with an outside surface of the rod and has magnetism so as to be conjoined with the outside surface of the rod due to a magnetic force, and a piezoelectric actuator which is disposed on one side of the driving force transmission member in the optical axis direction to provide an axis direction driving force to the rod via the driving force transmission member.

Abstract: A lens actuating module for realizing focus adjustment and optical zooming. The lens actuating module includes a rod which is disposed on one side of a lens barrel on which at least one lens is mounted, and has an axis direction corresponding to an optical axis direction of the lens barrel, a driving force transmission member which has a conjoining recess to be conjoined with an outside surface of the rod and has magnetism so as to be conjoined with the outside surface of the rod due to a magnetic force, and a piezoelectric actuator which is disposed on one side of the driving force transmission member in the optical axis direction to provide an axis direction driving force to the rod via the driving force transmission member.

Abstract: A lens actuating module for realizing focus adjustment and optical zooming. The lens actuating module includes a rod which is disposed on one side of a lens barrel on which at least one lens is mounted, and has an axis direction corresponding to an optical axis direction of the lens barrel, a driving force transmission member which has a conjoining recess to be conjoined with an outside surface of the rod and has magnetism so as to be conjoined with the outside surface of the rod due to a magnetic force, and a piezoelectric actuator which is disposed on one side of the driving force transmission member in the optical axis direction to provide an axis direction driving force to the rod via the driving force transmission member.

Abstract: The symmetric LDMOS transistor comprises a semiconductor substrate (1), a well (2) of a first type of conductivity in the substrate, and wells (3) of an opposite second type of conductivity. The wells (3) of the second type of conductivity are arranged at a distance from one another. Source/drain regions (4) are arranged in the wells of the second type of conductivity. A gate dielectric (7) is arranged on the substrate, and a gate electrode (8) on the gate dielectric. A doped region (10) of the second type of conductivity is arranged between the wells of the second type of conductivity at a distance from the wells. The gate electrode has a gap (9) above the doped region (10), and the gate electrode overlaps regions that are located between the wells (3) of the second type of conductivity and the doped region (10).

Abstract: A low cost integration method for a plurality of deep isolation trenches on the same chip is provided. The trenches have an additional n-type or p-type doped region surrounding the trench—silicon interface. Providing such variations of doping the trench interface is achieved by using implantation masking layers or doped glass films structured by a simple resist mask. By simple layout variation of the top dimension of the trench various trench depths at the same time can be ensured. Using this method, wider trenches will be deeper and smaller trenches will be shallower.

Abstract: The p-channel LDMOS transistor comprises a semiconductor substrate (1), an n well (2) of n-type conductivity in the substrate, and a p well (3) of p-type conductivity in the n well. A portion of the n well is located under the p well. A drain region (4) of p-type conductivity is arranged in the p well, and a source region (9) of p-type conductivity is arranged in the n well. A gate dielectric (7) is arranged on the substrate, and a gate electrode (8) is arranged on the gate dielectric. A body contact region (14) of n-type conductivity is arranged in the n well. A p implant region (17) is arranged in the n well under the p well in the vicinity of the p well. The p implant region locally compensates n-type dopants of the n well.

Abstract: A method of forming an isolation region is provided that in one embodiment substantially reduces divot formation. In one embodiment, the method includes providing a semiconductor substrate, forming a first pad dielectric layer on an upper surface of the semiconductor substrate and forming a trench through the first pad dielectric layer into the semiconductor substrate. In a following process sequence, the first pad dielectric layer is laterally etched to expose an upper surface of the semiconductor substrate that is adjacent the trench, and the trench is filled with a trench dielectric material, wherein the trench dielectric material extends atop the upper surface of the semiconductor substrate adjacent the trench and abuts the pad dielectric layer.