Abstract: Disclosed is a plasma etching chamber including a gas distribution plate guiding a reaction gas to the edge of the wafer; a plate disposed to be spaced apart from the gas distribution plate; and bumper portions protruding on at least one of opposite surfaces of the gas distribution plate and the plate to allow the pressure of the reaction gas moving to the edge of the wafer to be uniform.

Abstract: A method of forming an isolation region is provided that in one embodiment substantially reduces divot formation. In one embodiment, the method includes providing a semiconductor substrate, forming a first pad dielectric layer on an upper surface of the semiconductor substrate and forming a trench through the first pad dielectric layer into the semiconductor substrate. In a following process sequence, the first pad dielectric layer is laterally etched to expose an upper surface of the semiconductor substrate that is adjacent the trench, and the trench is filled with a trench dielectric material, wherein the trench dielectric material extends atop the upper surface of the semiconductor substrate adjacent the trench and abuts the pad dielectric layer.

Abstract: An n-conductively doped source region (2) in a deep p-conducting well (DP), a channel region (13), a drift region (14) formed by a counterdoping region (12), preferably below a gate field plate (6) insulated by a gate field oxide (8), and an n-conductively doped drain region (3) arranged in a deep n-conducting well (DN) are arranged in this order at a top side of a substrate (1). A lateral junction (11) between the deep p-conducting well (DP) and the deep n-conducting well (DN) is present in the drift path (14) in the vicinity of the drain region (3) so as to avoid a high voltage drop in the channel region (13) during the operation of the transistor and to achieve a high threshold voltage and also a high breakdown voltage between source and drain.

Abstract: A semiconductor body (10) comprises a field-effect transistor (11). The field-effect transistor (11) comprises a drain region (12) of a first conduction type, a source region (13) of the first conduction type, a drift region (16) and a channel region (14) of a second conduction type which is opposite to the first conduction type. The drift region (16) comprises at least two stripes (15, 32) of the first conduction type which extend from the drain region (12) in a direction towards the source region (13). The channel region (14) is arranged between the drift region (16) and the source region (13).

Abstract: A single-media multi-devices (SMMD) home server includes a plurality of media decoding units decoding multi-channel AV media data divided from a realistic media content and reproducing the decoded multi-channel AV media data; a home server processor unit dividing the realistic media content into the multi-channel AV media data and effects data, feeding the divided multi-channel AV media data to the media decoding units, and generating effects control data corresponding to the divided effects data; and a gateway/Ethernet switch receiving the realistic media content through a network and forwarding the received realistic media content to the home server processor unit, and receiving the divided multi-channel AV media data from the home server processor unit and feeding the received multi-channel AV media data to the media decoding units through a switching function.

Abstract: A high voltage NMOS transistor is disclosed where the p-doped body is isolated against the p-doped substrate by a DN well having a pinch-off region where the depth of the DN-well is at minimum. By the forming space charge region at raising drain potentials a shielding of the drain potential results because the space charge region touches the field oxide between source and drain at the pinch-off region. An operation at the high side at enhanced voltage levels is possible.

Abstract: A low cost integration method for a plurality of deep isolation trenches on the same chip is provided. The trenches have an additional n-type or p-type doped region surrounding the trench—silicon interface. Providing such variations of doping the trench interface is achieved by using implantation masking layers or doped glass films structured by a simple resist mask. By simple layout variation of the top dimension of the trench various trench depths at the same time can be ensured. Using this method, wider trenches will be deeper and smaller trenches will be shallower.

Abstract: Provided are an apparatus and method for modeling and analyzing a network simulation for a salable simulation framework (SSF)-based network simulation package. A system logic set is generated and a network simulation modeling suitable for a predetermined network application is formed according to the system logic set. The network simulation modeling is transmitted to a predetermined network simulation package that performs simulation. Statistical information is generated based on the result according to the system logic set. Complicated network simulation modeling errors can be minimized, and remodeling of the network simulation modeling can be reduced.

Abstract: The present invention relates to a hybrid superelastic metal-metal sulfide materials for current collector and anode of battery, which use two phase alloy of Ti—Ni or three phase alloy of Ti—Ni—X as current collector, and produce a Ti, Ni sulfide at a surface of current collector with an inside sulfide method to allow to use as an active materials of positive electrode, and perform a role of current collector and anode of battery with one material by endowing all materials with superelastic characteristic, and it have an excellent effect providing a hybrid superelastic metal-metal sulfide materials for current collector and anode having thin plate and fine wire shape.

Abstract: A high voltage-generating circuit comprises a control circuit for generating a control signal for executing an operation command and generating a refresh signal depending upon a refresh operation, an oscillator driven according to an enable signal, for outputting an oscillation signal the cycle of which is controlled according to a refresh signal, a charge pump circuit for generating a high voltage using a power source voltage according to the oscillation signal, wherein the charge pump circuit has the ascent rate of the high voltage controlled according to variation in the cycle of the oscillation signal, and a level detection circuit for comparing the high voltage and a reference voltage to determine whether the high voltage reaches a target value, and controlling the operation of the oscillator according to the result of the comparison.

Abstract: Disclosed related to a door for a refrigerator may include an outer door forming the front exterior; a cap decoration formed at the upper and lower sides of the outer door; a water pipe drawn into the door through the cap decoration and through which water flows; and a fixing member on which a depression part fixing the water pipe is formed.

Abstract: Provided is an RF front-end transceiver having an oscillator for outputting a resonant frequency signal whose frequency is controlled by a frequency control signal provided from a frequency synthesizer or a base band processor; a receive amplifier for amplifying and outputting a receive RF signal; a receive mixer for mixing the receive RF signal amplified and the resonant frequency signal to convert the receive RF signal into a receive base band signal; a transmit mixer for mixing a transmit base band signal and the resonant frequency signal to convert the transmit base band signal into a transmit RF signal; and a transmit amplifier for amplifying and outputting the transmit RF signal, wherein a resonant frequency of at least one of the receive amplifier, the receive mixer, the transmit mixer and the transmit amplifier is controlled by the frequency control signal.

Abstract: A semiconductor memory device having a delay circuit, the delay circuit is constructed in order for a refresh operation and a normal operation to have different delay paths such that a minimum tRAS (Active to Precharge command period) delay time of the refresh operation to which tRFC (Auto Referesh to Active/Auto Referesh command period) is applied is longer than a minimum tRAS delay time of a normal operation to which tRC (Active to Active/Auto Refresh command period) is applied. Thus, a greater noise margin is secured in tRFC in a refresh operation being the worst situation of a DRAM. Accordingly, the probability that fail can occur is reduced and the yield upon test is thus improved.

Abstract: A semiconductor memory device comprises a central control circuit for receiving an operation command from an external chipset, generating an active signal for executing the operation command, and generating a precharge signal after a predetermined time, a row path control circuit for controlling a bank according to the active signal or the precharge signal of the central control circuit, and a precharge time control circuit, which is enabled according to the active signal to output an oscillation signal having a predetermined frequency, divides the oscillation signal based on a setting time from when an active operation is performed until when a precharge operation is performed, and then outputs a precharge time control signal, thereby controlling generation of the precharge signal of the central control circuit.

Abstract: A semiconductor memory device comprises a central control circuit for receiving an operation command from an external chipset, generating an active signal for executing the operation command, and generating a precharge signal after a predetermined time, a row path control circuit for controlling a bank according to the active signal or the precharge signal of the central control circuit, and a precharge time control circuit, which is enabled according to the active signal to output an oscillation signal having a predetermined frequency, divides the oscillation signal based on a setting time from when an active operation is performed until when a precharge operation is performed, and then outputs a precharge time control signal, thereby controlling generation of the precharge signal of the central control circuit.

Abstract: Provided is an active load circuit of a voltage gain amplifier, which allows a high voltage gain with a low supply voltage operation in high-frequency range. The active load circuit includes a PMOS transistor which is connected between the amplifying unit and a power supply voltage and functions as a load element in a low frequency range; a negative feedback buffering unit which is connected to the gate of the PMOS transistor and functions as a common drain amplifier to stabilize the output voltage of the voltage gain amplifier and drive the voltage gain amplifier at a low voltage; and a capacitor which is connected to the negative feedback buffering unit and compensates for both an impedance and a frequency characteristics when the voltage gain amplifier operates in a high frequency range.

Abstract: The present invention relates to a semiconductor memory device. According to the present invention, a delay circuit is constructed in order for a refresh operation and a normal operation to have different delay paths such that a minimum tRAS (Active to Precharge command period) delay time of the refresh operation to which tRFC (Auto Referesh to Active/Auto Referesh command period) is applied is longer than a minimum tRAS delay time of a normal operation to which tRC (Active to Active/Auto Refresh command period) is applied. Thus, a greater noise margin is secured in tRFC in a refresh operation being the worst situation of a DRAM. Accordingly, the probability that fail can occur is reduced and the yield upon test is thus improved.

Abstract: A high voltage-generating circuit comprises a control circuit for generating a control signal for executing an operation command and generating a refresh signal depending upon a refresh operation, an oscillator driven according to an enable signal, for outputting an oscillation signal the cycle of which is controlled according to a refresh signal, a charge pump circuit for generating a high voltage using a power source voltage according to the oscillation signal, wherein the charge pump circuit has the ascent rate of the high voltage controlled according to variation in the cycle of the oscillation signal, and a level detection circuit for comparing the high voltage and a reference voltage to determine whether the high voltage reaches a target value, and controlling the operation of the oscillator according to the result of the comparison.

Abstract: The present invention relates to a cutting wheel with blanks which reduces vibration and frictional noise generated when a workpiece such as stone, steel concrete, asphalt, metal, ceramic, or wood is cut, and a method for manufacturing the same. There is provided a cutting wheel of which a wheel body is formed with at least one blank. The blank is shaped in a line with a variable width, and the blank is filled with noise absorbing material. According to the present invention, the noise and vibration is considerably decreased as compared with a general plane type cutting wheel and a conventional cutting wheel with blanks. In addition, the cutting wheel with blanks according to the present invention can absorb the noise and vibration as good as the sandwich type cutting wheel, and particularly, is considerably high in strength, and is inexpensive to manufacture with ½ to ? costs compared with the sandwich type cutting wheel.

Abstract: Provided is a pipelined folding analog-digital converter, the pipelined folding analog-digital converter comprising: a first sample-and-hold unit that samples and outputs a number of analog input voltages; a reference voltage generator that generates a number of reference voltages; a pre-amplifier that amplifies and outputs a number of values subtracting each reference voltage from the outputs of the first sample-and-hold unit, wherein an offset effect due to asymmetry of the amplifier is eliminated; a first folder that folds and outputs a number of outputs of the pre-amplifier; a second sample-and-hold unit that samples and outputs a number of outputs of the first folder; a second folder that folds and outputs a number of outputs of the second sample-and-hold unit; and a comparator that performs a comparison operation between the outputs of the pre-amplifier and the output values of the second folder to find a digital output value, whereby the offset caused by the device mismatch is removed, so that it is po