Abstract: A method for manufacturing a magnetic memory element structure using a Ru hard mask and a post pillar thermal annealing process. A Ru hard mask is formed over a plurality of memory element layers and an ion milling is performed to transfer the image of the Ru hard mask onto the underlying memory element layers. A high-angle ion milling an be performed to remove any redeposited material from the sides of the memory element layers, and a non-magnetic, dielectric material can be deposited. A thermal annealing process can then be performed to repair any damage caused by the previously performed ion milling processes.

Abstract: A method for manufacturing a magnetic memory element array that includes the use of a Ru hard mask layer and a diamond like carbon hard mask layer formed over the Ru hard mask layer. A plurality of magnetic memory element layers are deposited over a wafer and a Ru hard mask layer is deposited over the plurality of memory element layers. A layer of diamond like carbon is deposited over the Ru hard mask layer, and a photoresist mask is formed over the layer of diamond like carbon. A reactive ion etching is then performed to transfer the image of the photoresist mask onto the diamond like carbon mask, and an ion milling is performed to transfer the image of the patterned diamond like carbon mask onto the underlying Ru hard mask and memory element layers. The diamond like carbon mask can then be removed by reactive ion etching.

Abstract: Embodiments of the present invention facilitate efficient and effective increased memory cell density configuration. In one embodiment, a semiconductor device comprises: a first pillar magnetic tunnel junction (pMTJ) memory cell that comprises a first pMTJ located in a first level in the semiconductor device; and a second pillar magnetic tunnel junction (pMTJ) memory cell that comprises a second pMTJ located in a second level in the semiconductor device, wherein the second pMTJ location with respect to the first pMTJ is coordinated to comply with a reference pitch for the memory cell. A reference pitch is associated a first switch coupled to the first pMTJ and the second pitch reference component is a second switch coupled to the second pMTJ. The first switch and second switch can be transistors. The reference pitch coordination facilitates reduced pitch between memory cells and increased information storage capacity of bits per memory device area.

Abstract: A Magnetic Tunnel Junction (MTJ) device can include a second Precessional Spin Current (PSC) magnetic layer of Ruthenium (Re) having a predetermined thickness and a predetermined smoothness. An etching process for smoothing the PSC magnetic layer can be performed in-situ with various deposition processes after a high temperature annealing of the MTJ formation.

Abstract: A magnetic memory element for using in magnetic random access memory. The magnetic memory element includes a novel exchange coupling layer for use in an antiferromagnetic structure for magnetically pinning a magnetic reference layer of the memory element. The exchange coupling layer is located between a first magnetic layer (reference layer) and a second magnetic layer (keeper layer). The exchange coupling layer includes a layer of Ru located between first and second layers of Ir. The Ir layers can be in contact with each of the first and second magnetic layers to provide an interfacial magnetic anisotropy, as well as providing RKKY exchange field. The Ru layer, provides an increased RKKY exchange field as a result of the high RKKY exchange coupling of Ru.

Abstract: A Magnetic Tunnel Junction (MTJ) device can include a free magnetic layer having a predetermined smoothness. An etching process for smoothing the free magnetic layer can be performed in-situ with various deposition processes after a high temperature annealing of the MTJ formation.

Abstract: Embodiments of the present invention facilitate efficient and effective increased memory cell density configuration. In one embodiment, the method comprises: forming a first pitch reference component and a second pitch reference component; forming a first pillar magnetic tunnel junction (pMTJ) located in a first level and a second pMTJ located in a second level, wherein the location of the second pMTJ with respect to the first pMTJ is coordinated based upon a reference pitch distance between the first pitch reference component and first pitch reference component. In one exemplary implementation, the first pitch reference component is a first switch coupled to the first pMTJ and the second pitch reference component is a second switch coupled to the second pMTJ. The reference component size can be based upon a minimum lithographic processing dimension.

Abstract: A method for manufacturing a magnetic memory element structure using a Ru hard mask and a post pillar thermal annealing process. A Ru hard mask is formed over a plurality of memory element layers and an ion milling is performed to transfer the image of the Ru hard mask onto the underlying memory element layers. A high-angle ion milling an be performed to remove any redeposited material from the sides of the memory element layers, and a non-magnetic, dielectric material can be deposited. A thermal annealing process can then be performed to repair any damage caused by the previously performed ion milling processes.

Abstract: A method for manufacturing a magnetic memory element structure using a Ru hard mask and a self-aligned pillar formation process. A plurality of magnetic memory element layers are deposited over a substrate, including a magnetic reference layer, a non-magnetic barrier layer deposited over the magnetic reference layer, a magnetic free layer deposited over the non-magnetic barrier layer and a Ru hard mask layer deposited over the Ru hard mask layer. A mask structure is formed over the Ru hard mask and the image of the mask structure is transferred to the Ru hard mask. A first ion milling is performed to transfer the image of the patterned Ru hard mask onto the underlying magnetic free layer and non-magnetic barrier layer, the first ion milling being terminated when the magnetic reference layer has been reached. A non-magnetic dielectric protective layer is then deposited and a second ion milling is performed.

Abstract: A magnetic memory element having a Ru hard mask layer. The use of Ru advantageously allows for closer spacing of adjacent magnetic memory elements leading to increased data density. In addition, the use of Ru as a hard mask reduces parasitic electrical resistance by virtue of the fact that Ru does not oxidize in ordinary manufacturing environments. The magnetic memory element can be formed by depositing a plurality of memory element layers, depositing a Ru hard mask layer, depositing a RIEable layer over the Ru hard mask layer, and forming a photoresist mask over the hard mask layer. A reactive ion etching can be performed to transfer the image of the photoresist mask onto the RIEable layer to form a RIEable mask. An ion etching can then be performed to transfer the image of the RIAable mask onto the underlying Ru hard mask and underlying memory element layers.

Abstract: A method for manufacturing a magnetic memory element array that includes the use of a Ru hard mask layer and a diamond like carbon hard mask layer formed over the Ru hard mask layer. A plurality of magnetic memory element layers are deposited over a wafer and a Ru hard mask layer is deposited over the plurality of memory element layers. A layer of diamond like carbon is deposited over the Ru hard mask layer, and a photoresist mask is formed over the layer of diamond like carbon. A reactive ion etching is then performed to transfer the image of the photoresist mask onto the diamond like carbon mask, and an ion milling is performed to transfer the image of the patterned diamond like carbon mask onto the underlying Ru hard mask and memory element layers. The diamond like carbon mask can then be removed by reactive ion etching.

Abstract: A Magnetic Tunnel Junction (MTJ) device can include a second Precessional Spin Current (PSC) magnetic layer of Ruthenium (Re) having a predetermined thickness and a predetermined smoothness. An etching process for smoothing the PSC magnetic layer can be performed in-situ with various deposition processes after a high temperature annealing of the MTJ formation.

Abstract: A method for manufacturing a magnetic memory array provides back end of line annealing for associated processing circuitry without causing thermal damage to magnetic memory elements of the magnetic memory array. An array of magnetic memory element pillars is formed on a wafer, and the magnetic memory elements are surrounded by a dielectric isolation material. After the pillars have been formed and surrounded by the dielectric isolation material an annealing process is performed to both anneal the memory element pillars to form a desired grain structure in the memory element pillars and also to perform back end of line thermal processing for circuitry associated with the memory element array.

Abstract: A magnetic memory pillar structure having a plurality of magnetic memory elements connected in series, wherein switching of individual memory elements in the pillar structure can be accomplished based on differing switching current values of the magnetic memory elements. Each of the plurality of memory elements advantageously have similar retention values in spite of the different switching current values (latency values) as a result of a precessional spin current injection structure provided in the memory element or memory elements having the lower switching current value.

Abstract: A magnetoresistive random-access memory (MRAM) is disclosed. MRAM device has a magnetic tunnel junction stack having a significantly improved performance of the free layer in the magnetic tunnel junction structure. The MRAM device utilizes a precessional spin current (PSC) magnetic layer in conjunction with a perpendicular MTJ where the in-plane magnetization direction of the PSC magnetic layer is free to rotate. The precessional spin current magnetic layer is constructed with a material having a face centered cubic crystal structure, such as permalloy.

Abstract: A magnetic data recording element for magnetic random access memory data recording. The magnetic data recording element includes a magnetic tunnel junction element that includes a magnetic reference layer, a magnetic free layer and a non-magnetic barrier layer located between the non-magnetic reference layer and the magnetic free layer. The magnetic free layer includes a layer of Hf that causes the magnetic free layer to have an increased perpendicular magnetic anisotropy. This increased perpendicular magnetic anisotropy improves data retention and increases thermal stability, by preventing the magnetization of the magnetic free layer from inadvertently losing its magnetic orientation.

Abstract: A magnetoresistive random-access memory (MRAM) device is disclosed. The device described herein has a thermal stability enhancement layer over the free layer of a magnetic tunnel junction. The thermal stability enhancement layer improves the thermal stability of the free layer, increases the magnetic moment of the free layer, while also not causing the magnetic direction of the free layer to become in plan. The thermal stability enhancement layer can be comprised of a layer of CoFeB ferromagnetic material.

Abstract: A method for a photo and/or electron beam lithographic fabricating processes for producing a pillar array test device. The method includes receiving a wafer having a plurality of bit cells arranged in a grid and etching a plurality of bottom electrode traces to connect a plurality of bottom electrode pads in a centrally located bit cell to each of the bit cells in the grid. The method further includes fabricating an array of magnetic tunnel junction pillars onto each respective pad in the centrally located bit cell. The wafer is then planarized. The method further includes etching a plurality of top electrode traces to connect the plurality of magnetic tunnel junction pillars to each of the bit cells in the grid, and outputting the wafer for subsequent testing.

Abstract: Embodiments of the present invention include multiple independent terminals for a plurality of devices in a stack configuration within a semiconductor. In one embodiment, a semiconductor comprises: a first device at a first semiconductor level within a multi terminal device stack; wherein the first device is coupled to a first terminal; a second device at a second semiconductor level within the multi terminal device stack, wherein the second device is coupled to a second terminal; and a third terminal is coupled to the first device, wherein the first terminal and second terminal are independently coupled to the first device and second device respectively. The third terminal can be coupled to the second device. The first terminal, the second terminal, and third terminal and couple components included in the multi terminal stack to components not included in the multi terminal stack.

Abstract: Embodiments of the present invention include multiple independent terminals for a plurality of devices in a stack configuration within a semiconductor. In one embodiment, a multi terminal fabrication process comprises: performing an initial pillar layer formation process to create layers of a multi terminal stack; forming a first device in the layers of the multi terminal stack; forming a second device in the layers of the multi terminal stack; and constructing a set of terminals comprising: a first terminal coupled to the first device, a second terminal coupled to the second device; and a third terminal coupled to the first device; wherein at least two terminals in the set of terminals are independent. The third terminal can be coupled to the second device.