Patents by Inventor Mustafa Pinarbasi

Mustafa Pinarbasi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200083442
    Abstract: A magnetic memory element having a magnetic free layer and a magnetic reference layer with a non-magnetic barrier layer between the magnetic reference layer and the magnetic free layer. A spin current layer (which may be a precessional spin current layer) is located adjacent to the magnetic free layer and is separated from the magnetic free layer by a non-magnetic coupling layer. A material layer adjacent to and in contact with the spin current layer, has a material composition and thickness that are chosen to provide a desired effective magnetization in the spin current layer. The material layer, which may be a capping layer or a seed layer, can be constructed of a material other than tantalum which may include one or more of Zr, Mo, Ru, Rh, Pd, Hf, W, Ir, Pt and/or alloys and/or nitrides of these elements.
    Type: Application
    Filed: September 7, 2018
    Publication date: March 12, 2020
    Inventors: Jorge Vasquez, Bartlomiej Adam Kardasz, Wei Chen, Mustafa Pinarbasi
  • Patent number: 10580827
    Abstract: A magnetoresistive random-access memory (MRAM) is disclosed. The MRAM bit cell consists of a magnetic tunnel junction stack having a significantly improved performance of the magnetic storage layer. The MRAM device utilizes a polarizer layer with a magnetic vector that can switch between a stabilizing magnetic direction and a programming magnetic direction.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: March 3, 2020
    Assignee: Spin Memory, Inc.
    Inventors: Steven Watts, Georg Martin Wolf, Kadriye Deniz Bozdag, Bartlomiej Kardasz, Mustafa Pinarbasi
  • Publication number: 20200052034
    Abstract: A magnetic memory element for using in magnetic random access memory. The magnetic memory element includes a novel exchange coupling layer for use in an antiferromagnetic structure for magnetically pinning a magnetic reference layer of the memory element. The exchange coupling layer is located between a first magnetic layer (reference layer) and a second magnetic layer (keeper layer). The exchange coupling layer includes a layer of Ru located between first and second layers of Ir. The Ir layers can be in contact with each of the first and second magnetic layers to provide an interfacial magnetic anisotropy, as well as providing RKKY exchange field. The Ru layer, provides an increased RKKY exchange field as a result of the high RKKY exchange coupling of Ru.
    Type: Application
    Filed: August 8, 2018
    Publication date: February 13, 2020
    Inventors: Bartlomiej Adam Kardasz, Wei Chen, Jorge Vasquez, Mustafa Pinarbasi
  • Patent number: 10516094
    Abstract: A method for a photolithographic fabricating process to define pillars having small pitch and pillar size. The method includes coating a hard mask layer of a wafer with a photoresist. The wafer is exposed with a first line pattern comprising a plurality of parallel lines in a first direction. The wafer is then exposed with a second line pattern comprising a plurality of parallel lines in a second direction orthogonal to the first direction. The wafer is then developed to remove areas of the photoresist that were exposed by the first line pattern and the second line pattern resulting in a plurality of pillars.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: December 24, 2019
    Assignee: Spin Memory, Inc.
    Inventors: Prachi Shrivastava, Mustafa Pinarbasi, Thomas Boone
  • Publication number: 20190371997
    Abstract: A method for a photo and/or electron beam lithographic fabricating processes for producing a pillar array test device. The method includes receiving a wafer having a plurality of bit cells arranged in a grid and etching a plurality of bottom electrode traces to connect a plurality of bottom electrode pads in a centrally located bit cell to each of the bit cells in the grid. The method further includes fabricating an array of magnetic tunnel junction pillars onto each respective pad in the centrally located bit cell. The wafer is then planarized. The method further includes etching a plurality of top electrode traces to connect the plurality of magnetic tunnel junction pillars to each of the bit cells in the grid, and outputting the wafer for subsequent testing.
    Type: Application
    Filed: April 18, 2019
    Publication date: December 5, 2019
    Inventors: Pradeep Manandhar, Prachi Shrivastava, Mustafa Pinarbasi, Thomas Boone
  • Patent number: 10461242
    Abstract: A magnetic memory element for Magnetic Random Access Memory. The magnetic memory element has improved reference layer magnetic pinning. The magnetic memory element has a magnetic free layer, a magnetic reference layer and a non-magnetic barrier layer located between the magnetic free layer and the magnetic reference layer. The magnetic reference layer has a magnetic moment that is pinned in a perpendicular orientation through exchange coupling with a synthetic antiferromagnetic structure that includes first and second magnetic structures and an antiferromagnetic exchange coupling structure located between the first and second magnetic structures. The antiferromagnetic exchange coupling structure includes a layer of Ru located between first and second layers of Pt. The Pt layers in the antiferromagnetic exchange coupling structure advantageously increases the magnetic proximity effect at both Ru interfaces, which extends the exchange coupling range of the antiferromagnetic exchange coupling layer.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: October 29, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Bartlomiej Adam Kardasz, Jorge Vasquez, Mustafa Pinarbasi, Georg Wolf
  • Patent number: 10446742
    Abstract: A method for manufacturing a magnetic memory element array. A plurality of magnetic memory elements are formed on a substrate, and a dielectric fill layer such as SiO2 or SiNx is deposited over the magnetic memory element pillars. An ion milling is then performed at a high angle (at least 70 degrees) relative normal to remove topographic dielectric features from areas over the magnetic memory elements. Optionally, additional ion milling processes can be performed at increasing angles relative to normal until the dielectric material has been removed from the areas over the magnetic memory elements.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: October 15, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Marcin Gajek, Eric Michael Ryan, Mustafa Pinarbasi
  • Patent number: 10424723
    Abstract: A Magnetic Tunnel Junction (MTJ) device including pillar contacts coupling the free magnetic layer of cell pillars to a top contact. The pillar contacts are electrically isolated from one or more other portions of the cell pillar by one or more self-aligned sidewall insulators. The MTJ device further including one of a static magnetic compensation layer or an exchange spring layer in the cell pillar.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: September 24, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Thomas Boone, Pradeep Manandhar, Manfred Schabes, Bartlomiej Kardasz, Mustafa Pinarbasi
  • Patent number: 10411185
    Abstract: A method for a photo and/or electron beam lithographic fabricating processes for producing a pillar array test device. The method includes receiving a wafer having a plurality of bit cells arranged in a grid and etching a plurality of bottom electrode traces to connect a plurality of bottom electrode pads in a centrally located bit cell to each of the bit cells in the grid. The method further includes fabricating an array of magnetic tunnel junction pillars onto each respective pad in the centrally located bit cell. The wafer is then planarized. The method further includes etching a plurality of top electrode traces to connect the plurality of magnetic tunnel junction pillars to each of the bit cells in the grid, and outputting the wafer for subsequent testing.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: September 10, 2019
    Assignee: Spin Memory, Inc.
    Inventors: Pradeep Manandhar, Prachi Shrivastava, Mustafa Pinarbasi, Thomas Boone
  • Patent number: 10388860
    Abstract: A method for manufacturing magnetic random access memory. The method allows very high density magnetic memory elements to be formed on a magnetic memory chip. A magnetic memory element material is deposited and a diamond like carbon (DLC) hard mask is formed over the magnetic memory element material. An ion or atom bombardment process such as ion milling is performed to remove portions of the magnetic memory element material that are not protected by the hard mask to form a plurality of magnetic memory element pillars. Because the diamond like carbon hard mask is resistant to the material removal processes such as ion milling, it can be made very thin (10-20 nm), which reduces shadowing while still allowing a process such as ion milling to be used to define the magnetic data element pillars. This advantageously allows the pillars to be formed with well defined, vertical sidewalls, and avoiding shorting.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: August 20, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Elizabeth A. Dobisz, Girish Jagtiani, Yuan-Tung Chin, Thomas D. Boone, Mustafa Pinarbasi
  • Patent number: 10388853
    Abstract: A magnetic memory element for Magnetic Random Access Memory. The magnetic memory element has improved reference layer magnetic pinning and reduced dipole fringing field effect on the magnetic free layer. The magnetic memory element includes a magnetic reference layer having a pinned magnetization, a magnetic free layer having a switchable magnetization and a non-magnetic barrier layer between the magnetic reference layer and the magnetic free layer. The magnetic reference layer is exchange coupled with a synthetic anti-ferromagnetic structure that includes a first multi-layer structure, a second multi-layer structure and a non-magnetic anti-parallel exchange coupling layer located between the first and second multi-layer structures. Each of the first and second multi-layer structures includes a plurality of bi-layers of Pt and Co, with the Pt being deposited first and located below the Co.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: August 20, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Bartlomiej Adam Kardasz, Jorge Vasquez, Georg Wolf, Mustafa Pinarbasi
  • Patent number: 10381553
    Abstract: A magnetoresistive random-access memory (MRAM) device is disclosed. The device described herein has a thermal stability enhancement layer over the free layer of a magnetic tunnel junction. The thermal stability enhancement layer improves the thermal stability of the free layer, increases the magnetic moment of the free layer, while also not causing the magnetic direction of the free layer to become in plan. The thermal stability enhancement layer can be include a layer of CoFeB ferromagnetic material.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: August 13, 2019
    Assignee: Spin Transfer Technologies, Inc.
    Inventors: Mustafa Pinarbasi, Bartek Kardasz
  • Patent number: 10374153
    Abstract: A method for manufacturing a magnetic random access memory element that allows for improved magnetic element pillar formation in a high density magnetic memory element array. The method allows a magnetic memory element pillar to be formed by ion milling with a lower pillar height for reduced shadowing effect. A memory element seed layer and under-layer are first formed on a substrate and layer of electrically insulating material such as silicon oxide is deposited. A chemical mechanical polishing process is performed, leaving the seed layer and under-layer surrounded by a layer of electrically insulating material having an upper surface that is coplanar with an upper surface of the under-layer. A magnetic memory element pillar is formed over the seed layer and under-layer by depositing the magnetic memory element material, forming a mask over the magnetic memory element material and performing an ion milling process to form a magnetic memory element pillar.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: August 6, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Jorge Vasquez, Bartlomiej Adam Kardasz, Mustafa Pinarbasi, Girish Jagtiani
  • Patent number: 10374147
    Abstract: A magnetic data recording element for magnetic random access memory data recording. The magnetic data recording element includes a magnetic tunnel junction element that includes a magnetic reference layer, a magnetic free layer and a non-magnetic barrier layer located between the non-magnetic reference layer and the magnetic free layer. The magnetic reference layer includes a layer of Hf that causes the magnetic reference layer to have an increased perpendicular magnetic anisotropy. This increased perpendicular magnetic anisotropy improves reliability and stability of the magnetic data recording element by preventing loss of magnetic orientation of the magnetic reference layer such as during high writing current conditions.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: August 6, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Mustafa Pinarbasi, Bartlomiej Adam Kardasz, Jorge Vasquez, Manfred Ernst Schabes
  • Publication number: 20190237664
    Abstract: A Magnetic Tunnel Junction (MT) device can include a free magnetic layer having a predetermined smoothness. An etching process for smoothing the free magnetic layer can be performed in-situ with various deposition processes after a high temperature annealing of the MTJ formation.
    Type: Application
    Filed: March 8, 2019
    Publication date: August 1, 2019
    Inventors: Bartlomiej KARDASZ, Jorge VASQUEZ, Mustafa PINARBASI
  • Patent number: 10367136
    Abstract: A method for manufacturing a magnetic memory element for use in a magnetic random access memory device to form a MgO spin current coupling layer with improved spin current coupling and reduced device area resistance (RA). The method involves depositing a magnetic free layer structure, and then depositing a MgO spin current coupling layer over the magnetic free layer. The magnetic spin current coupling layer is deposited in a sputter deposition chamber using radio frequency (RF) power. The sputter deposition of the spin current coupling layer can be performed using a MgO target without intervening oxidation steps to form a continuous layer of MgO that is not a multilayer structure of Mg and intermittent oxidation layers. Because the MgO spin transport layer deposited by this RF sputtering does not affect RA of the device, the thickness of the MgO spin transport layer can be adjusted to optimize spin transport performance.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 30, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Bartlomiej Adam Kardasz, Jorge Vasquez, Mustafa Pinarbasi, Georg Wolf
  • Patent number: 10367139
    Abstract: A method of manufacturing a Magnetic Tunnel Junction (MTJ) device including pillar contacts coupling the free magnetic layer of MTJ pillars to a top contact. The pillar contacts are electrically isolated from one or more other portions of the MTJ pillar by one or more self-aligned sidewall insulators. The MTJ device further including one of a static magnetic compensation layer or an exchange spring layer in the MTJ pillar.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 30, 2019
    Assignee: Spin Memory, Inc.
    Inventors: Thomas Boone, Pradeep Manandhar, Manfred Schabes, Bartlomiej Kardasz, Mustafa Pinarbasi
  • Patent number: 10361359
    Abstract: A Magnetic Random Access Memory apparatus device having a memory element formed as a magnetic tunnel junction (MTJ) pillar and having a heating element for maintaining a desired minimum temperature of the memory element. The heating element is separated from the memory element by a thin, non-magnetic, electrically insulating wall, which can be constructed of alumina. The heating element is connected with circuitry that controllably delivers electrical current to the heating element to maintain a desired minimum temperature of the memory element.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: July 23, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Manfred Ernst Schabes, Thomas D. Boone, Mustafa Pinarbasi
  • Publication number: 20190214553
    Abstract: A method for manufacturing a magnetic memory element array. A plurality of magnetic memory elements are formed on a substrate, and a dielectric fill layer such as SiO2 or SiNx is deposited over the magnetic memory element pillars. An ion milling is then performed at a high angle (at least 70 degrees) relative normal to remove topographic dielectric features from areas over the magnetic memory elements. Optionally, additional ion milling processes can be performed at increasing angles relative to normal until the dielectric material has been removed from the areas over the magnetic memory elements.
    Type: Application
    Filed: January 9, 2018
    Publication date: July 11, 2019
    Inventors: Marcin Gajek, Eric Michael Ryan, Mustafa Pinarbasi
  • Publication number: 20190207103
    Abstract: Embodiments of the present invention facilitate efficient and effective increased memory cell density configuration. In one embodiment, the method comprises: forming a first pitch reference component and a second pitch reference component; forming a first pillar magnetic tunnel junction (pMTJ) located in a first level and a second pMTJ located in a second level, wherein the location of the second pMTJ with respect to the first pMTJ is coordinated based upon a reference pitch distance between the first pitch reference component and first pitch reference component. In one exemplary implementation, the first pitch reference component is a first switch coupled to the first pMTJ and the second pitch reference component is a second switch coupled to the second pMTJ. The reference component size can be based upon a minimum lithographic processing dimension.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Inventors: Mustafa PINARBASI, Thomas BOONE, Pirachi SHRIVASTAVA, Pradeep MANANDHAR