Abstract: To reduce the cost by reducing the number of parts and simplify the control of regeneration in the hydraulic actuator even though the meter-in control and the meter-out control can be performed separately while the supply and the discharge of hydraulic fluid is controlled. A meter-in valve that controls supply flow from a hydraulic pump into a hydraulic cylinder is provided, and meter-out switching valve that switches the direction of supply and discharge of the hydraulic oil into the hydraulic cylinder and controls the discharge flow from the hydraulic cylinder to the oil tank is installed on the down stream side of the meter-in valve, and further, a regeneration control valve is installed on the down stream side of the meter-out switching valve.

Abstract: To reduce the cost by reducing the number of parts and simplify the control of regeneration in the hydraulic actuator even though the meter-in control and the meter-out control can be performed separately while the supply and the discharge of hydraulic fluid is controlled. A meter-in valve that controls supply flow from a hydraulic pump into a hydraulic cylinder is provided, and meter-out switching valve that switches the direction of supply and discharge of the hydraulic oil into the hydraulic cylinder and controls the discharge flow from the hydraulic cylinder to the oil tank is installed on the down stream side of the meter-in valve, and further, a regeneration control valve is installed on the down stream side of the meter-out switching valve.

Abstract: In a static random access memory (SRAM) device having a hierarchical bit line architecture, a local sense amplifier (SA) circuit includes P-channel transistors which precharge local bit lines connected to memory cells, P-channel transistors each having a gate connected to a corresponding one of the local bit lines and a drain connected to a corresponding one of global bit lines, and N-channel transistors each having a gate connected to a corresponding one of the global bit lines and a drain connected to a corresponding one of the local bit lines. As a result, restore operation to a non-selected memory cell during write operation can be achieved without the need of a fine timing control, the speed of read operation by a feedback function can be increased, and the area can be reduced.

Abstract: A semiconductor memory device includes a memory cell array block including a plurality of memory cells each including a data holding circuit configured to store data using a first and a second circuit elements and a transistor configured to connect the data holding circuit and a bit line together, sense amplifiers connected to bit lines directly or via switches, and a dummy memory cell array including a plurality of dummy memory cells each having the same circuit configuration as that of the memory cell with respect to the element size and the layout configuration. The plurality of dummy memory cells each include at least one inverter circuit configuration, and are connected together by the inverter circuits being connected together in series. An output signal of the inverter circuit of one in the final stage of the dummy memory cells is an activation signal for the sense amplifiers.

Abstract: A semiconductor memory device includes a memory cell connected to a read bit line and a pair of write bit lines, and a data amplifier connected to the read bit line. A precharge potential resetting circuit uses a function of generating precharge potentials to the pair of write bit lines based on data of the memory cell amplified by the data amplifier to set the precharge potentials of the non-selected pair of write bit lines to have a potential relationship corresponding to the data stored by the memory cell. As a result, data destruction of the non-selected memory cell during write operation is reduced or prevented, and the speed of operation is increased and the area is reduced.

Abstract: In a static random access memory (SRAM) device having a hierarchical bit line architecture, a local sense amplifier (SA) circuit includes P-channel transistors which precharge local bit lines connected to memory cells, P-channel transistors each having a gate connected to a corresponding one of the local bit lines and a drain connected to a corresponding one of global bit lines, and N-channel transistors each having a gate connected to a corresponding one of the global bit lines and a drain connected to a corresponding one of the local bit lines. As a result, restore operation to a non-selected memory cell during write operation can be achieved without the need of a fine timing control, the speed of read operation by a feedback function can be increased, and the area can be reduced.

Abstract: A semiconductor memory device includes a memory cell array block including a plurality of memory cells each including a data holding circuit configured to store data using a first and a second circuit elements and a transistor configured to connect the data holding circuit and a bit line together, sense amplifiers connected to bit lines directly or via switches, and a dummy memory cell array including a plurality of dummy memory cells each having the same circuit configuration as that of the memory cell with respect to the element size and the layout configuration. The plurality of dummy memory cells each include at least one inverter circuit configuration, and are connected together by the inverter circuits being connected together in series. An output signal of the inverter circuit of one in the final stage of the dummy memory cells is an activation signal for the sense amplifiers.

Abstract: A semiconductor memory device includes a first inverter and a second inverter each having an input and an output, the output of each of the first and second inverters being connected to the input of the other so that data is stored, a CMOS switch configured to connect the input of the first inverter and a write bit line, a read MOS transistor having a gate connected to the output of the first inverter, and a MOS switch configured to connect the read MOS transistor to a read bit line. The first and second inverters have different sizes and are connected to different source power supplies.

Abstract: A technique is provided for achieving reduction in size of an electronic device with a power amplifier circuit, while enhancing the performance of the electronic device. An RF power module for a mobile communication device includes first and second semiconductor chips, a passive component, and first and second integrated passive components, which are mounted over a wiring board. In the first semiconductor chip, MISFET elements constituting power amplifier circuits for the GSM 900 and for the DCS 1800 are formed, and a control circuit is also formed. In the first integrated passive component, a low pass filter circuit for the GSM 900 is formed, and in the second integrated passive component, a low pass filter circuit for the DCS 1800 is formed. In the second semiconductor chip, antenna switch circuits for the GSM 900 and DCS 1800 are formed. Over the upper surface of the wiring board, the second semiconductor chip is disposed next to the first semiconductor chip between the integrated passive components.

Abstract: A semiconductor memory device includes a first inverter and a second inverter each having an input and an output, the output of each of the first and second inverters being connected to the input of the other so that data is stored, a CMOS switch configured to connect the input of the first inverter and a write bit line, a read MOS transistor having a gate connected to the output of the first inverter, and a MOS switch configured to connect the read MOS transistor to a read bit line. The first and second inverters have different sizes and are connected to different source power supplies.

Abstract: A semiconductor integrated circuit including on a single chip a plurality of circuit blocks and a plurality of internal power supply circuits for delivering a common supply voltage to the plurality of circuit blocks includes: a shared power supply interconnection for connecting the plurality of circuit blocks and the plurality of internal power supply circuits; and an external pad connected to the shared power supply interconnection. Whether or not each of the internal power supply circuits delivers the supply voltage is controlled by a certain power supply control signal.

Abstract: A technique is provided for achieving reduction in size of an electronic device with a power amplifier circuit, while enhancing the performance of the electronic device. An RF power module for a mobile communication device includes first and second semiconductor chips, a passive component, and first and second integrated passive components, which are mounted over a wiring board. In the first semiconductor chip, MISFET elements constituting power amplifier circuits for the GSM 900 and for the DCS 1800 are formed, and a control circuit is also formed. In the first integrated passive component, a low pass filter circuit for the GSM 900 is formed, and in the second integrated passive component, a low pass filter circuit for the DCS 1800 is formed. In the second semiconductor chip, antenna switch circuits for the GSM 900 and DCS 1800 are formed. Over the upper surface of the wiring board, the second semiconductor chip is disposed next to the first semiconductor chip between the integrated passive components.

Abstract: A technique is provided for achieving reduction in size of an electronic device with a power amplifier circuit, while enhancing the performance of the electronic device. An RF power module for a mobile communication device includes first and second semiconductor chips, a passive component, and first and second integrated passive components, which are mounted over a wiring board. In the first semiconductor chip, MISFET elements constituting power amplifier circuits for the GSM 900 and for the DCS 1800 are formed, and a control circuit is also formed. In the first integrated passive component, a low pass filter circuit for the GSM 900 is formed, and in the second integrated passive component, a low pass filter circuit for the DCS 1800 is formed. In the second semiconductor chip, antenna switch circuits for the GSM 900 and DCS 1800 are formed. Over the upper surface of the wiring board, the second semiconductor chip is disposed next to the first semiconductor chip between the integrated passive components.

Abstract: In a semiconductor storage device, such as a dynamic random access memory (DRAM), in which dynamic data is amplified and read on a bit line, a data line sense amplifier/write buffer connected to a data line of a memory array and a data line sense amplifier control signal generating logic circuit connected to a dummy data line of a dummy memory array are provided. A sense amplifier is activated in accordance with an output signal of the logic circuit.

Abstract: The semiconductor integrated circuit includes: a plurality of macro cells; and a serial-parallel conversion circuit for converting a serial signal inputted from outside to generate parallel selection control signals during testing, or an A/D conversion circuit for converting an analog signal inputted from outside to generate digital selection control signals during testing. One or more among, the plurality of macro cells are selected based on the selection control signals and brought to a test operation state.

Abstract: In a semiconductor storage device, such as a dynamic random access memory (DRAM), in which dynamic data is amplified and read on a bit line, a data line sense amplifier/write buffer connected to a data line of a memory array and a data line sense amplifier control signal generating logic circuit connected to a dummy data line of a dummy memory array are provided. A sense amplifier is activated in accordance with an output signal of the logic circuit.

Abstract: A semiconductor memory device is provided comprising precharge circuits corresponding to global data line pairs, but not a precharge circuit corresponding to a local data line pair. In a command waiting state, data line selection switches are controlled to be in a connected state, so that the local data line pair and the global data line pairs are precharged all together while being connected to each other. In a command executing state, one of the data line selection switches, the one being not required for command execution, is in an open state. Similarly, a semiconductor memory device comprising only a precharge circuit corresponding to a local data line pair can be provided.

Abstract: The semiconductor integrated circuit includes: a plurality of macro cells; and a serial-parallel conversion circuit for converting a serial signal inputted from outside to generate parallel selection control signals during testing, or an A/D conversion circuit for converting an analog signal inputted from outside to generate digital selection control signals during testing. One or more among, the plurality of macro cells are selected based on the selection control signals and brought to a test operation state.

Abstract: In a memory cell array, source lines are provided so that each of the source lines is connected to ones of memory cells which belong to adjacent two rows and a plurality of source bias control circuits for supplying a source bias potential which is higher than a ground potential and lower than a power supply potential are provided so as to correspond to the source lines, respectively. In an active period, the source bias control circuits perform potential control so that one or more of the source lines selected by row predecoders which are not connected to one of the memory cells which is to be read out are controlled to be in a state where the source bias potential is supplied.

Abstract: In a memory cell array, source lines are provided so that each of the source line is connected to ones of memory cells which belong to adjacent two rows and a plurality of source bias control circuits for supplying a source bias potential which is higher than a ground potential and lower than a power supply potential are provided so as to correspond to the source lines, respectively. During a stand-by period, each of the source lines is controlled to be in a state where the source bias potential is supplied and, during an active period, one or more of the source lines which are not connected to one of the memory cells which is to be read out are controlled to be in a state where the source bias potential is supplied.