Abstract: A semiconductor integrated circuit including on a single chip a plurality of circuit blocks and a plurality of internal power supply circuits for delivering a common supply voltage to the plurality of circuit blocks includes: a shared power supply interconnection for connecting the plurality of circuit blocks and the plurality of internal power supply circuits; and an external pad connected to the shared power supply interconnection. Whether or not each of the internal power supply circuits delivers the supply voltage is controlled by a certain power supply control signal.

Abstract: A technique is provided for achieving reduction in size of an electronic device with a power amplifier circuit, while enhancing the performance of the electronic device. An RF power module for a mobile communication device includes first and second semiconductor chips, a passive component, and first and second integrated passive components, which are mounted over a wiring board. In the first semiconductor chip, MISFET elements constituting power amplifier circuits for the GSM 900 and for the DCS 1800 are formed, and a control circuit is also formed. In the first integrated passive component, a low pass filter circuit for the GSM 900 is formed, and in the second integrated passive component, a low pass filter circuit for the DCS 1800 is formed. In the second semiconductor chip, antenna switch circuits for the GSM 900 and DCS 1800 are formed. Over the upper surface of the wiring board, the second semiconductor chip is disposed next to the first semiconductor chip between the integrated passive components.

Abstract: A semiconductor memory device is provided comprising precharge circuits corresponding to global data line pairs, but not a precharge circuit corresponding to a local data line pair. In a command waiting state, data line selection switches are controlled to be in a connected state, so that the local data line pair and the global data line pairs are precharged all together while being connected to each other. In a command executing state, one of the data line selection switches, the one being not required for command execution, is in an open state. Similarly, a semiconductor memory device comprising only a precharge circuit corresponding to a local data line pair can be provided.

Abstract: A logic circuit block and a memory circuit block are provided on a semiconductor chip. A timing adjustment circuit block for adjusting the propagation timing of signals is provided on a line between the circuit blocks. A timing adjustment circuit unit includes: a delay element block including a plurality of delay elements for adding different delay amounts to the inter-block signals; a counter circuit block for receiving a timing adjustment control signal from the timing adjustment circuit block; and a fuse circuit block in which a fuse is melted down based on a fuse information signal held by the counter circuit block after a timing verification and which replaces the function of the counter circuit block.

Abstract: Source potential connection transistors, each supplying a source control potential from a source potential wiring to a source node, are disposed so as to be dispersed in a memory cell array. In addition, a source potential control circuit is disposed inside a row decoder block. With this configuration, the number of the cells connected to each word line can be increased, and the area of the memory core can be reduced. Furthermore, the pattern shape of the diffusion layer constituting the source potential connection transistor is made the same as that of the diffusion layer of a memory cell transistor, whereby mask creation can be facilitated.

Abstract: In a memory cell array, source lines are provided so that each of the source lines is connected to ones of memory cells which belong to adjacent two rows and a plurality of source bias control circuits for supplying a source bias potential which is higher than a ground potential and lower than a power supply potential are provided so as to correspond to the source lines, respectively. In an active period, the source bias control circuits perform potential control so that one or more of the source lines selected by row predecoders which are not connected to one of the memory cells which is to be read out are controlled to be in a state where the source bias potential is supplied.

Abstract: In a memory cell array, source lines are provided so that each of the source line is connected to ones of memory cells which belong to adjacent two rows and a plurality of source bias control circuits for supplying a source bias potential which is higher than a ground potential and lower than a power supply potential are provided so as to correspond to the source lines, respectively. During a stand-by period, each of the source lines is controlled to be in a state where the source bias potential is supplied and, during an active period, one or more of the source lines which are not connected to one of the memory cells which is to be read out are controlled to be in a state where the source bias potential is supplied.

Abstract: A semiconductor memory device 1 comprises precharge circuits 31, 32 corresponding to global data line pairs DL0/NDL0, DL1/NDL1, but not a precharge circuit corresponding to a local data line pair LDL/NLDL. In a command waiting state, data line selection switches 21, 22 are controlled to be in a connected state, so that the local data line pair and the global data line pairs are precharged all together while being connected to each other. In a command executing state, one of the data line selection switches 21, 22, the one being not required for command execution, is in an open state. Similarly, a semiconductor memory device comprising only a precharge circuit corresponding to a local data line pair can be provided.

Abstract: A semiconductor integrated circuit device including a plurality of internal power supply generating circuits arranged on a single chip and a common monitor pad is provided. The internal power supply generating circuits are connected via respective switches to the common monitor pad, and the internal power supply generating circuits and the monitor pad are selectively connectable using the switches.

Abstract: Logic circuits access a memory block by way of an access circuit. The memory block, which is formed of a mixed configuration of DRAMs and an SRAM, realizes the desired memory space. A data output register is provided at the output side of the SRAM so as to synchronize data output timing from the DRAMs with data output timing from the SRAM.

Abstract: A port A of the path including a first transistor of a memory cell to be accessed, a first bit line pair, a first column selection switch and a data line pair interleaves with a port B of the path including a second transistor of the memory cell to be accessed, a second bit line pair, a second column selection switch and the data line pair in two cycles of a clock. A read amplifier amplifies data transferred from a bit line pair to the data line pair and outputs the resultant data to an input/output buffer in one cycle of the clock. The input/output buffer outputs the data received from the read amplifier to the outside in one cycle of the clock.

Abstract: A plurality of logic circuits access a DRAM block by way of an access circuit. The operation clock for the DRAM block is set at a higher frequency than the system clock for the logic circuits. Outputs of a first bit width from the logic circuits are subjected to serial/parallel conversion into data of a second bit width and the data is written into the DRAM block.

Abstract: A semiconductor memory device 1 comprises precharge circuits 31, 32 corresponding to global data line pairs DL0/NDL0, DL1/NDL1, but not a precharge circuit corresponding to a local data line pair LDL/NLDL. In a command waiting state, data line selection switches 21, 22 are controlled to be in a connected state, so that the local data line pair and the global data line pairs are precharged all together while being connected to each other. In a command executing state, one of the data line selection switches 21, 22, the one being not required for command execution, is in an open state. Similarly, a semiconductor memory device comprising only a precharge circuit corresponding to a local data line pair can be provided.

Abstract: Logic circuits access a memory block by way of an access circuit. The memory block, which is formed of a mixed configuration of DRAMs and an SRAM, realizes the desired memory space. A data output register is provided at the output side of the SRAM so as to synchronize data output timing from the DRAMs with data output timing from the SRAM.

Abstract: A large capacity DRAM block, which is accessible by a logic circuit, includes a VBB/VPP power supply circuit. The other DRAM blocks accessible by a logic circuit share the VBB/VPP power supply circuit of the large capacity DRAM block as their VBB/VPP power supply circuit.

Abstract: A plurality of logic circuits both access the DRAM block by way of an access circuit. The operation clock for the DRAM block is set at a higher frequency than the system clock for the logic circuits. Outputs of a first bit width from the logic circuits are subjected to serial/parallel conversion into data of a second bit width and the data is written into the DRAM block.

Abstract: In recent system LSIs, a plurality of RAMs differing in capacity and in bit width have come to be mounted on a single chip according to the needs on the system side. However, when testing the plurality of RAMs, if the RAMs differ in capacity, they cannot be tested using the same test pattern (for example, HALF-MARCH) even if a special pin is provided for each RAM, because X, Y address mapping differs between the different RAMs; accordingly, the test has to be performed by dividing the RAMs into groups each consisting of RAMs having the same memory space, and this has lead to increased test time. An external address signal and a test-only address signal are provided as RAM control signals and, in the latter case, the number of X, Y addresses in each of the RAMs 4 and 5 is set equal to that of the largest capacity RAM 3 within the same chip, thereby making the X, Y address mapping the same for all the RAMs 3 to 5.

Abstract: A port A of the path including a first transistor of a memory cell to be accessed, a first bit line pair, a first column selection switch and a data line pair interleaves with a port B of the path including a second transistor of the memory cell to be accessed, a second bit line pair, a second column selection switch and the data line pair in two cycles of a clock. A read amplifier amplifies data transferred from a bit line pair to the data line pair and outputs the resultant data to an input/output buffer in one cycle of the clock. The input/output buffer outputs the data received from the read amplifier to the outside in one cycle of the clock.

Abstract: A semiconductor memory device has a plurality of memory cells each having a first transistor, a second transistor having a source or drain connected to one portion of the source or drain of the first transistor, and a third transistor having a source or drain connected to the other portion of the source or drain of the first transistor. The first transistor accumulates, in the channel thereof, charges transferred from the second and third transistors.

Abstract: A logic circuit block and a memory circuit block are provided on a semiconductor chip. A timing adjustment circuit block for adjusting the propagation timing of signals is provided on a line between the circuit blocks. A timing adjustment circuit unit includes: a delay element block including a plurality of delay elements for adding different delay amounts to the inter-block signals; a counter circuit block for receiving a timing adjustment control signal from the timing adjustment circuit block; and a fuse circuit block in which a fuse is melted down based on a fuse information signal held by the counter circuit block after a timing verification and which replaces the function of the counter circuit block.