Abstract: In recent system LSIs, a plurality of RAMs differing in capacity and in bit width have come to be mounted on a single chip according to the needs on the system side. However, when testing the plurality of RAMs, if the RAMs differ in capacity, they cannot be tested using the same test pattern (for example, HALF-MARCH) even if a special pin is provided for each RAM, because X, Y address mapping differs between the different RAMs; accordingly, the test has to be performed by dividing the RAMs into groups each consisting of RAMs having the same memory space, and this has lead to increased test time. An external address signal and a test-only address signal are provided as RAM control signals and, in the latter case, the number of X, Y addresses in each of the RAMs 4 and 5 is set equal to that of the largest capacity RAM 3 within the same chip, thereby making the X, Y address mapping the same for all the RAMs 3 to 5.

Abstract: A semiconductor memory device includes: a memory cell configured with two transistors and one capacitor; two word drivers for controlling two word lines alternately, the two word lines controlling reading/writing with respect to the memory cell; two address latch circuits for latching a first address signal to select one of the word drivers, the two address latch circuits being respectively provided upstream from the two word drivers; and an address decoder for decoding a second address signal to generate the first address signal. In this device, the address decoder supplies the first address signal in common to both of the two address latch circuits.

Abstract: A port A of the path including a first transistor of a memory cell to be accessed, a first bit line pair, a first column selection switch and a data line pair interleaves with a port B of the path including a second transistor of the memory cell to be accessed, a second bit line pair, a second column selection switch and the data line pair in two cycles of a clock. A read amplifier amplifies data transferred from a bit line pair to the data line pair and outputs the resultant data to an input/output buffer in one cycle of the clock. The input/output buffer outputs the data received from the read amplifier to the outside in one cycle of the clock.

Abstract: A semiconductor integrated circuit device including a plurality of internal power supply generating circuits arranged on a single chip and a common monitor pad is provided. The internal power supply generating circuits are connected via respective switches to the common monitor pad, and the internal power supply generating circuits and the monitor pad are selectively connectable using the switches.

Abstract: A semiconductor memory device includes: a memory cell configured with two transistors and one capacitor; two word drivers for controlling two word lines alternately, the two word lines controlling reading/writing with respect to the memory cell; two address latch circuits for latching a first address signal to select one of the word drivers, the two address latch circuits being respectively provided upstream from the two word drivers; and an address decoder for decoding a second address signal to generate the first address signal. In this device, the address decoder supplies the first address signal in common to both of the two address latch circuits.

Abstract: A semiconductor memory device has a plurality of memory cells each having a first transistor, a second transistor having a source or drain connected to one portion of the source or drain of the first transistor, and a third transistor having a source or drain connected to the other portion of the source or drain of the first transistor. The first transistor accumulates, in the channel thereof, charges transferred from the second and third transistors.

Abstract: A port A of the path including a first transistor of a memory cell to be accessed, a first bit line pair, a first column selection switch and a data line pair interleaves with a port B of the path including a second transistor of the memory cell to be accessed, a second bit line pair, a second column selection switch and the data line pair in two cycles of a clock. A read amplifier amplifies data transferred from a bit line pair to the data line pair and outputs the resultant data to an input/output buffer in one cycle of the clock. The input/output buffer outputs the data received from the read amplifier to the outside in one cycle of the clock.

Abstract: A semiconductor memory device allowing for high-speed random accesses and yet requiring no external refreshing by performing internal refreshing automatically and efficiently. If no external commands /RE or /WT, instructing that data should be read out or written on a memory cell, are given, the output signal of a first AND gate is asserted. A second AND gate is provided to obtain a logical product of the output signal of the first AND gate and an internal refresh signal INTREF representing that refreshing may be performed internally and independently. The output signal REFEN of the second AND gate is used as a reference signal for automatic refreshing. Thus, refreshing is performed automatically by taking advantage of a window during which no external commands are input. And when an external command is input, refreshing is canceled.

Abstract: Redundancy function with excellent repair efficiency is implemented by specifying a single address for a semiconductor memory device of a multi-bit accessing type. A memory array includes a plurality of memory segments associated with respective addresses. Each memory segment is coupled to a data bus multiplexer via an associated first data bus. A sub-data bus, which includes a larger number of signal lines than that of those included in the first data bus, is provided for each memory segment. These signal lines are connected to associated bit lines in each memory sub-array. A data bus switching circuit is associated with each memory segment to electrically connect the respective signal lines included in the first data bus to the counterparts included in the sub-data bus to meet a predetermined relationship by cutting one of fuses off. In this manner, redundancy function with excellent repair efficiency is implementable on a bit-by-bit basis, not on an address basis.

Abstract: In a semiconductor memory device with multiple memory cells, each including a charge storage device and two transfer devices for transferring its charge, these memory cells are accessible with no select signal provided externally. The memory device includes a clock generator for generating first and second mutually complementary clock signals. In response to the first and second clock signals, one of first word lines and one of second word lines are activated alternately. Specifically, the first clock signal makes a memory cell accessible through a first bit line by activating the first word line and first transistor, while the second clock signal makes the memory cell accessible through a second bit line by activating the second word line and second transistor.

Abstract: The semiconductor storage device of this invention includes memory cells each having two transistors and one storage capacitor. Each memory cell is connected with a first word line and a first bit line for a first port and a second word line and a second bit line for a second port. The first and second bit lines are alternately disposed in an open bit line configuration. In the operation of the semiconductor storage device, in a period when a first precharge signal for precharging each first bit line or a first sense amplifier activating signal for activating a first sense amplifier is kept in an active state, a second precharge signal for precharging each second bit line and a second sense amplifier activating signal for activating a second sense amplifier are both placed in an inactive state.

Abstract: A cache memory including a first memory array and a main memory including a second memory array are integrated together on the same semiconductor substrate. Each memory cell in the first memory array is of a 2Tr1C type including: first and second transistors, the sources of which are connected together; and a data storage capacitor, one of the two electrodes of which is connected to the common source of the first and second transistors. Each memory cell in the second memory array is of a 1Tr1C type including: a third transistor; and a data storage capacitor, one of the two electrodes of which is connected to the source of the third transistor.

Abstract: Over an active region with two bent portions on a semiconductor substrate, first and second word lines extend to cross these bent portions and to be vertically spaced apart from each other. Around at the center of the active region, a capacitor for storing data thereon and a capacitor contact are formed. A first bit line contact, which is connected to the active region, is formed on the opposite side to the capacitor contact across the first word line over the active region. A second bit line contact, which is also connected to the active region, is formed on the opposite side to the capacitor contact across the second word line over the active region. These first and second bit line contacts are provided substantially symmetrically about the center of the memory cell. In a pair of memory cells adjacent to each other along bit lines, one vertical end of the active region in one of the memory cells is continuous with an associated vertical end of the active region in the other memory cell.

Abstract: An electromagnetic induction device which comprises a split-type core assembly comprising at least one winding formed thereon and first and second core segments each having at least two joint faces spaced apart from each other, the first and second core segments are connected together with the joint faces of one of the first and second core segments held in contact with the joint faces of the other of the first and second core segments, and a finely divided ferromagnetic material is interposed between the joint faces of the respective first and second core segments. The ferromagnetic material used has an average particle size sufficient to form a magnetic fluid medium.

Abstract: An apparatus and method for producing a filament harness which comprises feeding a plurality of strands in a downstream direction onto a support which receives the strands. There is a head which contacts the strands and a control means for causing relative motion between the support and the head to form the plurality of wires into a predetermined, desired pattern. In addition, the product produced by the method is also disclosed.

Abstract: An improved method of operating an apparatus to cut sheet material workpieces eliminates the inadvertent dropping of a relatively small scrap or remainder portion of a workpiece into a clearance space between a pair of cutter blades and a discharge conveyor. Thus, a relatively large sheet metal workpiece is gripped by a holder which moves the workpiece relative to a pair of blades. The blades are moved relative to each other to cut the workpiece to form a product having a desired configuration. The product is dropped onto a discharge conveyor. In order to prevent a relatively small scrap piece remaining in the holder from being dropped into a space between the discharge conveyor and the blades, the holder is extended through the space between the blades to a location over the discharge conveyor and is opened to drop the scrap or remainder portion of the workpiece onto the discharge conveyor.

Abstract: A sheet metal workpiece is held by holders as the workpiece is cut and moved relative to a device such as a shearing machine or punch press. An improved apparatus and method is provided to precisely position the sheet metal workpiece relative to the holders. This apparatus includes a first gripper assembly which is disposed at an opening in a support structure for the sheet metal workpiece. The first gripper assembly moves the workpiece to position it along a first axis. A second gripper assembly is disposed at another opening in the support structure and moves the workpiece to position it along a second axis which extends transversely to the first axis. The two gripper assemblies can be moved between extended positions projecting upwardly from the support structure and retracted positions in which the gripper assemblies are disposed within the support structure.