Patents by Inventor Naoki Yasuda

Naoki Yasuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9379256
    Abstract: A nonvolatile semiconductor memory device includes a charge storage layer on a first insulating film, a second insulating film which is provided on the charge storage layer, formed of layers, and a control gate electrode on the second insulating film. The second insulating film includes a bottom layer (A) provided just above the charge storage layer, a top layer (C) provided just below the control gate electrode, and a middle layer (B) provided between the bottom layer (A) and the top layer (C). The middle layer (B) has higher barrier height and lower dielectric constant than both the bottom layer (A) and the top layer (C). The average coordination number of the middle layer (B) is smaller than both the average coordination number of the top layer (C) and the average coordination number of the bottom layer (A).
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: June 28, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Naoki Yasuda
  • Publication number: 20160155750
    Abstract: According to one embodiment, a semiconductor memory device includes a multilayer body, a semiconductor body, a charge accumulation film, a top oxide film, a silicon nitrogen-containing film, a bottom oxide film, and a block insulating film. The multilayer body includes a plurality of electrode films separately stacked each other and a plurality of interelectrode insulating films disposed between the plurality of electrode films. The semiconductor body that penetrates the multilayer body, extends in stacking direction of the multilayer body. The silicon nitrogen-containing film provides between the semiconductor body and the interelectrode insulating film and between the semiconductor body and the top oxide film and containing silicon and nitrogen. In the silicon nitrogen-containing film, thickness of a portion located between the electrode film and the body is thinner than thickness of a portion located between the interelectrode insulating film and the body.
    Type: Application
    Filed: March 9, 2015
    Publication date: June 2, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Naoki YASUDA
  • Patent number: 9323484
    Abstract: A print instruction apparatus includes a group information acquisition unit that acquires information identifying a feeder unit included in a group including two or more feeder units, from among a plurality of feeder units mounted on a printer to feed paper sheets, where if one feeder unit in the group runs out of paper sheets during printing, another feeder unit in the same group is configured to feed paper sheets, and a display that acquires information related to a remaining amount of paper sheets each of the feeder units in the group, and displays information related to a total remaining amount of paper sheets in the group.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: April 26, 2016
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Hiroo Yoshida, Yutaka Kojima, Shinichi Takano, Taro Yamazaki, Masayuki Iwasawa, Naoki Yasuda, Issei Matsushita, Shingo Kato
  • Publication number: 20160104802
    Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.
    Type: Application
    Filed: December 16, 2015
    Publication date: April 14, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masao SHINGU, Jun FUJIKI, Naoki YASUDA, Koichi MURAOKA
  • Publication number: 20160087109
    Abstract: A nonvolatile semiconductor memory device includes a charge storage layer on a first insulating film, a second insulating film which is provided on the charge storage layer, formed of layers, and a control gate electrode on the second insulating film. The second insulating film includes a bottom layer (A) provided just above the charge storage layer, a top layer (C) provided just below the control gate electrode, and a middle layer (B) provided between the bottom layer (A) and the top layer (C). The middle layer (B) has higher barrier height and lower dielectric constant than both the bottom layer (A) and the top layer (C). The average coordination number of the middle layer (B) is smaller than both the average coordination number of the top layer (C) and the average coordination number of the bottom layer (A).
    Type: Application
    Filed: November 12, 2015
    Publication date: March 24, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Naoki YASUDA
  • Publication number: 20160079271
    Abstract: According to one embodiment, a control gate is formed on the semiconductor substrate and includes a cylindrical through hole. A block insulating film, a charge storage film, a tunnel insulating film, and a semiconductor layer are formed on a side surface of the control gate inside the through hole. The tunnel insulating film comprises a first insulating film having SiO2 as a base material and containing an element that lowers a band gap of the base material by being added. A density and a density gradient of the element monotonously increase from the semiconductor layer toward the charge storage film.
    Type: Application
    Filed: November 18, 2015
    Publication date: March 17, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Naoki YASUDA, Masaru KITO
  • Publication number: 20160079269
    Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises a plurality of conductive layers stacked in a first direction via an inter-layer insulating layer. In addition, the nonvolatile semiconductor memory device comprises: a semiconductor layer having the first direction as a longer direction; a tunnel insulating layer contacting a side surface of the semiconductor layer; a charge accumulation layer contacting a side surface of the tunnel insulating layer; and a block insulating layer contacting a portion facing the conductive layer, of a side surface of the charge accumulation layer. Moreover, the portion facing the conductive layer, of the charge accumulation layer is thinner compared to a portion facing the inter-layer insulating layer, of the charge accumulation layer.
    Type: Application
    Filed: July 14, 2015
    Publication date: March 17, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Katsuyuki SEKINE, Masaaki Higuchi, Masao Shingu, Hirokazu Ishigaki, Naoki Yasuda
  • Publication number: 20160079263
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode members and a plurality of insulating members, each of the electrode members and each of the insulating members being stacked alternately in a first direction on the substrate. The semiconductor memory device also includes a memory hole that extends in the stacked body in the first direction and a semiconductor member that is disposed to extend in the memory hole in the first direction. The semiconductor memory device also includes a memory member that is disposed between the semiconductor member and the plurality of electrode members. The plurality of electrode members including a first electrode member and a second electrode member, a thickness of the memory member at the position of the first electrode member being greater than a thickness of the memory member at the position of the second electrode member.
    Type: Application
    Filed: March 12, 2015
    Publication date: March 17, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Naoki YASUDA
  • Patent number: 9287288
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers and a plurality of insulating layers each provided between adjacent ones of the electrode layers; and a columnar portion penetrating through the stacked body and extending in a stacking direction of the stacked body. The columnar portion includes a channel body extending in the stacking direction; a charge storage film provided between the channel body and the electrode layer; and a gap provided between the charge storage film and the electrode layer.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: March 15, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoki Yasuda, Yoshiaki Fukuzumi
  • Patent number: 9252290
    Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: February 2, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masao Shingu, Jun Fujiki, Naoki Yasuda, Koichi Muraoka
  • Patent number: 9252291
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a first memory portion. The first memory portion includes a first base semiconductor layer, a first electrode, a first channel semiconductor layer, a first base tunnel insulating film, a first channel tunnel insulating, a first charge retention layer and a first block insulating film. The first channel semiconductor layer is provided between the first base semiconductor layer and the first electrode, and includes a first channel portion. The first base tunnel insulating film is provided between the first base semiconductor layer and the first channel semiconductor layer. The first channel tunnel insulating film is provided between the first electrode and the first channel portion. The first charge retention layer is provided between the first electrode and the first channel tunnel insulating film. The first block insulating film is provided between the first electrode and the first charge retention layer.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: February 2, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jun Fujiki, Naoki Yasuda, Daisuke Matsushita
  • Patent number: 9246014
    Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: January 26, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masao Shingu, Jun Fujiki, Naoki Yasuda, Koichi Muraoka
  • Publication number: 20160005755
    Abstract: According to one embodiment, a non-volatile memory device includes first electrodes, at least one first semiconductor layer, a first memory film, second electrodes, at least one second semiconductor layer, and a second memory film. The first electrodes are stacked in a first direction. The one first semiconductor layer extends in the first direction through the first electrodes. The first memory film is provided between each of the first electrodes and the one first semiconductor layer. The second electrodes are stacked in the first direction and provided together with the first electrodes in a second direction orthogonal to the first direction. The one second semiconductor layer extends in the first direction through the second electrodes. The second memory film is provided between each of the second electrodes and the one second semiconductor layer. An outer diameter of the first memory film is larger than that of the second memory film.
    Type: Application
    Filed: October 23, 2014
    Publication date: January 7, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Naoki YASUDA
  • Patent number: 9231116
    Abstract: A nonvolatile semiconductor memory device includes a charge storage layer on a first insulating film, a second insulating film which is provided on the charge storage layer, formed of layers, and a control gate electrode on the second insulating film. The second insulating film includes a bottom layer (A) provided just above the charge storage layer, a top layer (C) provided just below the control gate electrode, and a middle layer (B) provided between the bottom layer (A) and the top layer (C). The middle layer (B) has higher barrier height and lower dielectric constant than both the bottom layer (A) and the top layer (C). The average coordination number of the middle layer (B) is smaller than both the average coordination number of the top layer (C) and the average coordination number of the bottom layer (A).
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: January 5, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Naoki Yasuda
  • Patent number: 9224875
    Abstract: According to one embodiment, a control gate is formed on the semiconductor substrate and includes a cylindrical through hole. A block insulating film, a charge storage film, a tunnel insulating film, and a semiconductor layer are formed on a side surface of the control gate inside the through hole. The tunnel insulating film comprises a first insulating film having SiO2 as a base material and containing an element that lowers a band gap of the base material by being added. A density and a density gradient of the element monotonously increase from the semiconductor layer toward the charge storage film.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: December 29, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Naoki Yasuda, Masaru Kito
  • Publication number: 20150345046
    Abstract: A CVD device equipped with a container chamber (100) having an interior space (100a), and containing a substrate in a manner such that the film formation surface thereof faces upward from the bottom side (fifth region (A5)) of the interior space (100a). Silane gas and propane gas are supplied to the interior space (100a). A stainless-steel ceiling (120) is provided on the top of the interior space (100a). The ceiling (120) is provided with first through third partition members (171-173) attached thereto which comprise stainless steel, are positioned so as to extend in the -Z-direction and transect the X-direction, and divide the top side of the interior space (100a) into first through fourth regions (A1-A4). The substrate positioned inside the interior space (100a) is heated to 1600° C. The first through third partition members (171-173) and the ceiling (120) are cooled to 300° C. or lower by a cooling mechanism.
    Type: Application
    Filed: December 11, 2013
    Publication date: December 3, 2015
    Applicant: SHOWA DENKO K.K.
    Inventors: Daisuke MUTO, Yusuke KIMURA, Tomoya UTASHIRO, Seiichi TAKAHASHI, Kenji MOMOSE, Hisanori KURIBAYASHI, Naoki YASUDA
  • Patent number: 9196629
    Abstract: A memory string includes: a first semiconductor layer formed in a columnar shape extending in a stacking direction perpendicular to a substrate; a tunnel insulating film formed surrounding a side surface of the first semiconductor layer; a charge accumulation film formed surrounding the tunnel insulating film and configured to be capable of accumulating charges; a block insulating film formed surrounding the charge accumulation film; and a plurality of first conductive layers formed surrounding the block insulating film and disposed at a predetermined interval in the stacking direction. The first semiconductor layer comprises carbon-doped silicon and being formed to have different carbon concentrations in upper and lower portions in the stacking direction.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: November 24, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Haruka Sakuma, Shuichi Toriyama, Masumi Saitoh, Yoshiaki Fukuzumi, Naoki Yasuda
  • Patent number: 9142686
    Abstract: A nonvolatile semiconductor memory device includes a charge storage layer on a first insulating film, a second insulating film which is provided on the charge storage layer, formed of layers, and a control gate electrode on the second insulating film. The second insulating film includes a bottom layer (A) provided just above the charge storage layer, a top layer (C) provided just below the control gate electrode, and a middle layer (B) provided between the bottom layer (A) and the top layer (C). The middle layer (B) has higher barrier height and lower dielectric constant than both the bottom layer (A) and the top layer (C). The average coordination number of the middle layer (B) is smaller than both the average coordination number of the top layer (C) and the average coordination number of the bottom layer (A).
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: September 22, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Naoki Yasuda
  • Publication number: 20150263036
    Abstract: According to one embodiment, the columnar section includes a first region having a first diameter and a second region having a second diameter smaller than the first diameter. The plurality of electrode layers include a first electrode layer adjacent to the first region and a second electrode layer adjacent to the first region, and a third electrode layer adjacent to the second region and a fourth electrode layer adjacent to the second region. A distance between the third electrode layer and the fourth electrode layer is smaller than a distance between the first electrode layer and the second electrode layer.
    Type: Application
    Filed: March 2, 2015
    Publication date: September 17, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Naoki YASUDA, Hideaki Aochi
  • Publication number: 20150254541
    Abstract: A print instruction apparatus includes a group information acquisition unit that acquires information identifying a feeder unit included in a group that includes two or more feeder units, from among feeder units arranged in a printer to feed paper sheets, and that is configured in a manner such that if one of the feeder units in the group runs out of paper sheets in a printing of the printer, another feeder unit in the group starts to feed paper sheets, and a display that acquires information related to a remaining amount of paper sheets or information related to an out-of-paper state in each of the feeder units in the group that is configured to feed paper sheets in the printing operation, and that displays information related to a feeder unit in the group that is to be replenished with paper sheets.
    Type: Application
    Filed: September 15, 2014
    Publication date: September 10, 2015
    Applicant: FUJI XEROX CO., LTD.
    Inventors: Hiroo YOSHIDA, Shinichi TAKANO, Yutaka KOJIMA, Masayuki IWASAWA, Taro YAMAZAKI, Naoki YASUDA, Issei MATSUSHITA, Shingo KATO